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DIGffAt ~ F . ->, ' In this chapter, we '11 discover' how gates and inverters are combined to perform unique aµd specific logic functions. - .......... ,t,~ LESSON 6: COMBINATIONAL LOGIC CIRCUITS By Louis E. Frenzel A combinational logic circuit is a collection of gates and inverters that performs some specific logic function. A combinational logic circuit has two or more inputs and one or more outputs. The output is dependent upon the types of logic circuits used and how they are interconnected. The output is also a function of the binary input states. The operation of such a circuit is generally expressed in the form of a truth table where the binary states of the inputs are listed, as well as the corresponding outputs. Fig.1 is a block diagram of a combinational logic circuit, showing its inputs, outputs and the related truth table. As you might suspect, there is an enormous number of ways that you can interconnect gates and inverters to form various combinational logic circuits. On the other hand, there are many commonly used combinational logic circuits; so common, in fact, that manufacturers have constructed them in MSI and LSI form, thereby eliminating the need for the user to intercon- nect individual gates and inverters. Some of the more common logic circuits include decoders, multiplexers, demultiplexers, exclusive OR gates, and many others. When one of the standard -circuits cannot be used, custom logic circuits for special applications can be built with programmable logic arrays (PLAs). PLAs are a type of LSI circuit that permit a designer to interconnect arrays of AND gates, OR gates, and inverters within a single chip to produce a desired logic function. When you complete this lesson, you will have a working knowledge of all the most commonly used combinational logic circuits, including PLAs. New Logic Symbols Before proceeding to a discussion of combinational logic circuits, we want to introduce some of the newer symbols used to represent logic circuits in schematic diagrams. By now, you are already familiar with the symbols for AND, NAND, OR, NOR and other circuits. Those commonly used symbols are illustrated in Fig.2. Such logic symbols have been used for many years, but now are gradually being replaced by newer symbols. _ _ _ : }OUTPUTS COMBINATIONAL LOGIC CIRCUIT Fig.1: general block diagram of a combinational logic circuit and its related truth table. =D- =D- =D-- =D- ANO A B C X y 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 1 0 0 0 1 0 1 0 1 0 0 0 NANO -p,INVERTER (NOT) OR NOR Fig.2: the old and still most commonly used logic symbols. JK FLIP-FLOP APillL 1988 81 =E}- -0- =GOR AND INVERTER (NOT) =8NAND JK FLIP-FLOP Fig.3: the new logic symbols are easier to draw. The new symbols are shown in Fig.3. As you can see, each symbol is nothing more than a square block with input lines on the left, output lines on the right, and some designation in the block that tells what it does. A triangle at the output means inversion or the complement. A triangle at the input signifies that the input must go low to initiate the operation (active low input). Note the use of ampersand for AND and 1 for OR. We will be using the new logic symbols, as well the old ones, in the various circuits to be described to help you become familiar with them. In addition, other new logic symbols will be introduced, along with some of the combinational logic circuits as they are discussed. Decoders A decoder is a binary number detector; ie, it recognises the existence of one particular binary number. If the binary number for which the circuit is set up appears at its inputs, the decoder output will be a binary 1. For any other binary-input number, the decoder output will be binary O. The primary element in a decoder is an AND gate. Naturally, a NAND gate can be used as a decoder if an active low output is satisfactory. For example, suppose you wish to detect the presence of the two-bit binary number AB, where A = 1 and B = 1. All you have to do is apply those two bits to an AND gate as shown in Fig.4a. When those two bits are present, the output of the AND gate is binary 1. If any other two-bit combination appears at the input, of course, the output will be binary 0. Now suppose we wish to detect the two-bit binary number AB where A = 0 and B = 1. Again, we use an AND gate for this purpose. However, there is a problem here because if either input is binary 0, the output of the gate will be binary O as well. To eliminate that problem, we simply put an inverter between the desired input signal which has the value binary O and the input to the decoder AND gate. This is illustrated in Fig.4b. Now, when the binary number 01 appears at the decoder input, the inverter turns the binary O into a binary 1, so that the output from the AND gate is also binary 1, thereby indicating the presence of the number. Fig.5a shows how you would decode the binary number 0110. A 4-bit number requires a 4-input AND gate. Inverters are used on the two lines whose inputs are 0. Fig.5b shows an 8-input AND gate used to detect the presence of a specific byte, in this case 00111010. Note the use of inverters at the appropriate points. Also note that this decoder is a NAND gate. Therefore, when the correct number appears at the input, the output of the gate will be a binary Oinstead of a binary 1. While decoders are often implemented with individual gates, usually it is desirable to decode all possible states of a given binary word size. For example, a 2-bit binary number has four possible states, 00, 01, 10 and 11 or AB, AB, AB and AB. A separate 2-input AND gate is used to detect each one. Inverters are used at the inputs to provide the complement signals where necessary. Fig.6 shows a decoder of that type. The two-input lines are decoded into four possible outputs. As a result, such a circuit is ~om~times called a two-line to four-line decoder. Keep m mmd, however, that only one output will be binary 1 at any given time. Depending upon the input word applied, only one AND gate will be activated and only one output will be high. For that reason, a decoder circuit such as that is often referred to as a 1-of-4 decoder. The inputs and outputs of such a circuit are illustrated in the truth tabla of Fig.6. A popular MSI decoder circuit is a 3-line to 8-line 0 0 OR 0 0 OR & 0 A=D-r B (a) . & (a) lb) Fig.4: simple decoder circuits using old and new symbols. 82 SIUCO N CIIII' Fig.5: four-bit (A) and eight-bit (B) decoder circuits using the old and new logic symbols. lb) AB = W AB =X AB = Y AB A B w X y z 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 1 1 1 =Z Fig.6: a two-line to four-line combinational logic circuit (or one-of-four decoder circuit) and its truth table. decoder as illustrated in Fig, 7. The inputs are A, B and C. The outputs are labelled Y0-Y7. Such a decoder is often referred to as an octal decoder because is has eight outputs. You will also hear such a decoder referred to as a 1-of-8 decoder. In this circuit, NAND gates are used; therefore, the output of the gate will go low when it recognises a specific 3-bit input code. In other YO A Y1 Y2 SELECT INPUTS 8 Y3 DATA OUTPUTS C words, in this circuit all output lines are high except for one, which is the gate that is the decoding the correct input. Note that the circuit has three control inputs also. Those control inputs are used to enable or disable all of the decoder gates. To enable the circuit, Gl must be high and G2A and G2B must be low. The new logic symbol for this circuit is also shown in Fig.7. Note the designation BIN/OCT which means "binary in and octal out". Also, notice the "&" box, which defines the control inputs. Other popular decoders include the BCD-to-decimal decoder and the hexadecimal (hex) decoder. The former accepts the standard 4-line BCD input and activates one of its ten outputs, 0-9. This circuit is also referred to as a 4-line-to-10-line or 1-of-10 decoder. The hex decoder is a 4-line-to-16-line or 1-of-16 circuit. Both are available as MSI !Cs. Multiplexers Another widely used combinational logic circuit is the multiplexer. A multiplexer is an electronic switch that allows the selection of one of several input signals. Also called a data selector, the multiplexer chooses one of the inputs and passes it through to a single output. The circuit is essentially equivalent to a multi-pole selector switch as shown in Fig.8. A digital version of a multiplexer is created with AND and OR gates. The AND gates are used to select one of several inputs, while their outputs are ORed together to generate a single output. Such a multiplexer with four inputs is illustrated in Fig.9. Only one of the four AND gates will be enabled at a given time and its output will be passed through the OR gate to form the output. Such a circuit is referred to as a 1-of-4 data selector. Y4 2 Y5 0 6 7 .8 r ENABLE INPUTS Y7 b oo/r 0 INPUTS Y6 b OUTPUT INPUT 7 IS SELECTED Fig.8: an e quivalent circuit for a multiplexer. 628 G1 01 xv 02 BIN/OCT A ~ L B Y1 XY INPUTS OUTPUT DJ xv Y2 Y3 04 XY Y4 EQUIVALENT T / ~ YO G1 G2A Y5 & Y6 Y7 628 2-LINE TO 4-LINE DECODER NEW SYMBOL Fig.7: an octal or 1-of-8 decoder circuit shown in the old and new logic symbols. X y ADDRESS Fig.9: a 1-of-4 selector or multiplexer. APHIL 1988 83 Free Teletext! Yep, the Teletext transmissions are yours absoutely free of charge, courtesy of your local TV station (not in all areas - sorry!). All you need is a Teletext decoder to pick up the latest news, sports results, financial info, stocks and shares, recipes, etc. Build your own Teletext decoder - it works through your VCR so you save a fortune. Complete with hand controllers. Cat K-6315 Radio Direction Finder Here's a great first "big" project. When you've finished mucking around, build an amplifier! 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Electrical, 28 Station St, 61 1861 • Broken Hill: Hobbies & Electronics, 31 Oxide St. 88 4098 • Charlestown : Newtronics. 131 Pacific Hwy, 43 9600 • Catts Harbour: Coffs Harbour Electronics, Shop 3 Catts Habour Malt, Pa rk Ave, 52 5684 • Oeniliquin: Deni Electronics. 220 Cressy St. 8 1 3672 • Dubbo: Chris's Hi-Fi , 1/ 100 Talbragar Street. 82 871 1 • Forster: Forster Village Electronics, Shop 36, Forster Shopping Village, Breese Pde, 54 5006 • Griffith : Miatronics , 166- 170 Ban na Ave, 62 4534 • lnverell : Lyn Willing Electronics. 32 Lawrence St, 22 182 1 • Leaton : Leeton Record Centre, 12 1 Pine Ave, 53 2081 • Moree: Moree Electronics . 26 Balo St. 52 3458 • Parkes: Strad Music Centre, 279-281 Clarinda Stree!, 62 3366 • Port Macquarie : Hall of Electronics, The Horton Centre, 124 Horton St, 83 7440 • Orange: Fyfe Electronics, 296 Summer St, 62 64 91 • Taree: Brad's Electro nics. Shop 6. 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Oueen Elizabeth Drive, 58 2107 • Kawan a: Splitec , Shop 5, Ca rtwright Centre , Nicklin Way , 94 7349 • Mackay: Stevens Electronics . 42 Victo ri a St, 5 1 1723 • Maryborough : Ke ller Electronics, 218 Adelaide St. 21 4559 • Mt Isa: Outback Eteclrc riic-s, Shop 71, Barkl y Hwy, 43 3475• Nambour: Nambour Electronics , Shop 4, Lewan House, An n St, 41 1004 • SA• Mt Gambier: Hutchessons Communications Centre, 5 Elizabeth Sl , 25 0400• Murray Bridge: Bridge Communications, 246 Aclelaide Rd , 32 6476 •WA • Geraldton: Batavia Liphting & Electrical, 98a Chapman Rd , 23 184 2 • Harvey: Harvey Sales& Hi re Services, 94 Udur. Road. 291819 • Kalgoorlie: Todays Electronics. 295 Hannah Street, 21 5212 • Karratha: Dave's Oscitro nics, t st Floor , Savings House, Hedln nd Place . 85 4836 • Port Hedland : Ivan Tomek Electronics, 30 Anderson Street, 73 253 1 • TAS • Devon port : A.1. Electronics & Hobbies. 165 William St. Fourways 24 8322 •NT• Alice Springs: Farmer E!eclronics, 3 1 Elder St, 52 2380 ELECTRONICS cuit. Note also that both normal (Y) and complement (W-bar) outputs are available. The old and new logic symbols are illustrated. Demultiplexer A demultiplexer is simply the opposite of a multiplexer. It has a single input and multiple outputs. It is equivalent to the data selector switch shown in Fig.12. An electronic 4-output demultiplexer - the 74139 2-line to 4-line demultiplexer which contains two identical circuits - is illustrated in Fig.13. Acommon input line [enable) is connected to each of four AND gates through an inverter. The additional inputs on each NAND gate are used for decoding. Inputs A i; DC • i- Dl DATA 2 ' J I ' ' )-- t-- D2 I I I ' }- o-03 ' ' ' Fig.10: the 74173 integrated circuit is a dual selector/multiplexer combinational logic circuit. 86 SILICON CHIP -- ~ ' ,,..._ D5 To select the desired input, a 2-line-to-4-line (1-of-4) decoder circuit is used. It accepts two control inputs, X and Y, that arm an address (0 to 3 or binary 00 to binary 11 ). Depending upon which of the four input codes are applied, one of the four inputs will be selected. For example, if the address is binary 10, gate C will be enabled and D3 will pass through to the output. In practice, a separate decoder is not required because the AND gates used for selecting the inputs can also serve double duty as decoders. Fig.10 illustrates how 4-input AND gates can be used to form a 4-to-1 multiplexer - in this case, a dual 1-of-4 dataselector/multiplexer. The upper and lower multiplexers shown in Fig.10 are identical. Control lines A and B form the address, which is applied in various combinations to the AND gates. Notice also that inputs to be selected (IC0 through IC3 and 2C0 through 2C3) are also applied to each gate. Finally, the fourth input of each AND gate is connected to a single common line and an inverter. That line is used for enabling or disabling the entire circuit. When the 1G input is low, the upper multiplexer is enabled. When the 2G input is low, the lower multiplexer is enabled. Larger multiplexers can also be constructed. An 8-input multiplexer or 1-of-8 data selector is shown in Fig.11. A 3-bit address (ABC) is used to select one of the inputs D0-D7. Common line G-bar enables the cir- - ,- i D4 . D6 07 A DATA SELECT (BINARY){ I . ~ B C ' I .. ..__ ..___ ' DATA INPUTS .' I ·- t:t= J-- ' ·' ' ' J .... . c MUX A B DO y D1 02 w D3 04 05 D6 07 Fig.11: a 74151 1-of-8 data selector/multiplexer integrated circuit chip is illustrated using the old and new logic symbols. y w INCLUSIVE OR Jc,___ ,------o 0 EXCLUSIVE OR :.=:D--C=A+B ----1D-- -- A ---/. B C= AB+AB 2 INPUT ~ J o---4 OUTPUTS o---s Fig.12: a demultiplexer equivalent circuit. and B form an address, which enables one of the four gates. Therefore, the single input will be passed through the AND gate that is enabled. If you look carefully at Fig.13, you will see that this circuit is for all purposes a 2-to-4 line decoder. The only difference is that a common input line (enable) is shared by each of the gates. When used as a demultiplexer, the signal to be distributed to one or mor13 of the outputs is applied to that input line. When used as a decoder, the input can simply be ignored or used to enable or disable the circuit. Exclusive OR Gate The OR gate that we discussed previously is a logic circuit with two or more inputs and a single output. Its output is a binary 1 if any one or both inputs are binary 1. The proper name for such a circuit is inclusive OR. However, it is possible to construct an exclusive-OR circuit. An exclusive-OR or XOR gate, as it is referred to, has two inputs and a single output. Its output is binary 1 if one or the other, but not both, of its inputs are binary 1. A truth table for that circuit is shown in Fig.14 along with the symbols used to represent it. Compare the truth table for the exclusive OR to the truth table for the inclusive OR gate. The designation inside the new logic symbol ( - 1) designates the XOR function. In Fig.14, note the Boolean logic expressions for the output of the XOR circuit. In one version, the exclusive A B C A B C 0 0 0 0 1 1 1 1 0 1 1 1 0 0 1 1 0 1 0 1 0 1 1 0 Fig.14: the inclusive OR and exclusive OR (XOR) gates. Note difference in truth table when both inputs are binary 1. OR function is designated by a positive sign with a circle around it. You will often see. the expression for an XOR written in that way. Using the standard Boolean algebra expression for this circuit, you can easily see a way to implement it with standard AND gates, OR gates, and inverters. A typical circuit is shown in Fig.15A. A standard 2-input NAND gate can also be used to construct an XOR circuit. Two other approaches are illustrated in Fig.15b and 15c. Both perform exactly the same function, but in slightly different ways. The circuit in Fig.15b requires five gates, two connected as inverters. The circuit of Fig.15c can be made from a single quad 2-input NAND IC such as the 7400. In practice, it is not usually necessary to implement your own XOR circuits with gates like this. Complete XOR circuits are available already prepackaged in several IC forms. The common configuration is four XOR circuits per chip. An example is the 7486 TTL IC. XOR Applications True/Complement Circuit - Fig.16 shows how you can use an XOR gate to construct a true/complement circuit. That circuit accepts a 4-bit binary number DO-D3. Each bit is applied to one input of an XOR gate. All of the other XOR gate inputs are connected together to form a common control line. C =Aii + AB =A(±) B 1YO ENABLE 16 1Y1 (a) 1Y2 SELECT INPUTS 1A 1Y3 18 DATA OUTPUTS 2YO ENABLE 26 2Y1 2Y2 2A SELECT INPUTS 2Y3 28 Fig.13: a 74139 dual 2-line to 4-line demultiplexer. (C) Fig,15: three ways to implement an XOR gate. i\l'/ll/, 1988 87 I I I I ~___,I E3 E3 TRUE (NORMAL) OR COMPLEMENT OUTPUTS - Fig.16: true/complement circuit using XOR gates. C= :_ __,)[)o--c :__ .......,□i----- Aii + AB A B C 0 0 0 1 0 1 1 0 0 0 , 1 Fig.17: here are three ways to illustrate an exclusive NOR (XNOR) gate. If the control line is held at binary O level, the 4-bit binary word will simply pass through the gates and appear at the output unmodified or in "true" form. However, if the control line is made binary 1, the 4-bit word will be inverted by the XOR gates. The complement of the 4-bit input word will appear at the outputs. Comparators - A comparator is a circuit that compar_es ~inary numbers and generates an output signal mdicatmg when they are equal. A simple comparator can be constructed with a variation of the standard exclusive OR gate. Such a circuit is known as the exclusive NOR or XNOR. It is simply an XOR gate with an inverter at its output. Fig.17 illustrates the logic symbols used for this circuit. Also shown is the truth table for the circuit. Note that whe~ two inputs are equal (either both binary O or both bmary 1), then the output is binary 1, signaling the fact that they are equal. When the two inputs are opposite of one another, the circuit output is binary o. As you can see, the XNOR circuit is a simple 1-bit comparator. Comparator circuits for multi-bit binary words can be ~armed by using multiple XNOR gates and ANDing their outputs together as shown in Fig.18. That circuit is a 4-bit binary comparator. It compares two 4-bit words. One word is represented by bits X1-X4, while the other word is represented by bits Y1-Y4. The corresponding bits in each word are applied to an XNOR circuit. Fig.18: a 4-bit binary comparator combinational circuit. 88 SILICON CHIP ODD Fig.19: a simple 4-bit parity generator. CONTROL 0 = OUTPUT TRUE 1 = OUTPUT COMPLEMENT _,)D----[>o- PARITY BIT ) ~ ~ U T P U T EVEN 4-BIT WORD IN REGISTER 7486 A_ _ )D----~' If all the bits in the two words are equal, the output from each XNOR circuit will be binary 1. Therefore, ~he outpu_t from the AND gate will be binary 1, signalmg equality. If any one or more of the bits in the word are different, then one or more of the XNOR outputs will be binary O and the AND gate output will be zero, signaling inequality. To compare larger words, simply a?d more XN_O_R circuits, one for each pair of input bits, and additional AND gate inputs. As with most other types of combinational logic circuits, it is not necessary to build such comparators yourself. Once again, standard MSI comparator ICs are available and are widely used for address comparison in computer memories and peripheral interface circuits. Parity Checker/Generator - XOR circuits are also ?-sed in parity generator and checker circuits. Parity is a system of error detection sometimes used in digital circuits. As a binary word is transferred from one circuit to another or otherwise manipulated, bit errors can occur. One of the bits in a number that should be binary 1 could be transmitted as a binary O or vice versa because of some intermittent circuit fault or noise glitch. The resulting data will, therefore, be incorrect and could cause problems. For example, errors frequently occur when data is stored in or read out of a memory circuit. Parity generator and checker circuits can be used for detecting such errors. The parity system causes one additional bit to be added to a binary word for the purpose of detecting errors. If the total number of binary 1's in the number plus the yarity bit is odd, then we are said to be using odd parity. On the other hand, if the total number of binary 1 's in t~e number plus the parity bit is even, then we are usmg even parity. Some examples of odd and even parity are illustrated below. Look them over to be sure that you understand the concept. 10110001 10110001 11001110 11001110 1 0 0 1 Odd Parity Even Parity Odd Parity Even Parity XOR circuits are used in the parity generating proces~. The circuit shown in Fig.19 shows a simple 4-bit parity generator/checker circuit. Each XOR circuit l~oks_at a pair of bits and generates a new signal, indicatmg that the bits are the same or different Those output signals are, in turn, connected to XOR circuits and the process is repeated until a single output is ?enerated. That circuit generates a parity bit, which is added to the binary word from which it was g~ne~ated. ~ote t~at an inverter at the output of the circmt provides either odd or even parity. Once a parity bit has been generated, it is usually transmitted and/or stored along with the binary word. At the receiving end, another parity generator circuit looks at the received word and a new parity bit is generated. The new parity bit is then compared with the one that was transmitted. That is done in, an XNOR circuit. If the two bits are the same, then no transmission error has occurred. However, if the generated and received parity bits are different, an error is indicated. That signal can then be used to indicate an error condition and possibly initiate some corrective action. As with previous circuits, parity generator/ checker circuits are available in integrated form and need not be seperately constructed from XOR gates. Binary Adder - The main processing circuit in a digital computer or microprocessor is referred to as an arithmetic logic unit [ALU). At the heart of the ALU is a binary adder that permits the computer or microprocessor to perform addition, subtraction and other arithmetic operations. It is the exclusive OR circuit that forms the base for the binary adder circuit. The addition of binary numbers is a simple process. The rules are illustrated below. 0 0 1 1 A +o +1 0 1 +0 1 +1 10 +B C A+B=C Using those rules, you can easily 0 0 0 see how two multi-bit binary 1 1 0 numbers can be added. The ex1 0 1 1 0 1 amples below show how it is done. Work through the examples yourself to be sure that you understand how carry operations are dealt with. 6 +10 16 0110 +1010 10000 25 +26 51 11001 +11010 110011 To produce binary addition, we need a circuit that carries out the rules illustrated above. If you assume that each of the rules of binary addition shown above represent an entry into a truth table, you will see that an exclusive OR circuit is defined. The carry operation can be performed with a simple AND gate, Therefore, an XOR circuit and an AND gate together form a simple 1-bit binary adder, normally referred to as a halfadder, as shown in Fig.20. er? :--~--CD-suM ,m,oo, Fig.20: the half-adder circuit uses just one AND gate and one XOR gate. The reason it is called a half-adder is that it only adds two bits and does not take into consideration the need to add in a carry should it be necessary. To accomplish this, two half-adder circuits are combined to form a full-adder circuit as shown in Fig.21. Here the half-adder made up of gates A and B adds the two input bits. The sum is added to any carry input that might be present. That's accomplished with the halfadder made up of gates C and D. Gate Eis an OR gate that simply creates a carry-out signal for the next stage. Fig.21. a full-adder combinational circuit. FULL ADDER B c o - - - -- Cl Q ii Kt-+-OC CLOCK Fig.22: a serial full-adder for 8-bit words. A single bit full adder such as this can be used to add multibit binary numbers. That can be done by storing the numbers in shift registers, then shifting the numbers out a bit at a time in synchronism with a clock, as illustrated in Fig.22. Here, two 8-bit shift registers hold the numbers to be added. The adder generates the sum of the corresponding bits in the shift registers a bit at a time as the clock pulses shift the word out. The resulting sum is fed back to the input of the upper register for storage. To avoid the loss of the carry signal generated by each pair, a flipflop is connected to the carry output of the adder circuit. The flipflop is used to store the carry temporarily so that it can be added into the next bit position as needed. Rarely are serial adders like this used any more. Instead, multiple adder circuits are used so that the addition of parallel binary words can be accomplished. Fig.23 shows a parallel adder for two 4-bit binary numbers A0-A3 and B0-B3. The corresponding bits in each word are applied to each adder. Note how the carry output of one adder is fed to the carry input of the next adder. Also note that only a half-adder is required in the least significant bit position as there is no carry in. Four-bit parallel adders like this are available in S2 S3 so S1 LSB co co 83 A3 FULL ADDER 82 A2 Cl 81 Al BO AO Fig.23: a parallel full-adder circuit for two 4-bit numbers. APRIL 1988 89 INPUTS X = FUSIBLE LINK CONNECTED OUTPUTS Fig.24: a generalised circuit for a programmable logic array. MSI circuit form. Most of those circuits are extremely sophisticated and perform not only addition but also subtraction, as well as many other logic functions. Such circuits are used as the basis for an arithmetic logic unit (ALU) in digital computers. Programmable Logic Arrays While a high percentage of digital applications can be implemented with the combinational logic circuits just discussed, there are also many applications that require special circuits. Those special circuits can often be made from the available combinational circuits, plus random gates and inverters as required. While the resulting circuit usually performs the desired function, a good number of chips must be U8- Serviceman' S Log continued from pag-e 90 which is, I believe, still the original material. When I think of the times a solid state MHA gets blown out by lightning, or zapped by some illegal CB afterburner, I wonder why they ever stopped making valve type MHAs. My friend was lucky to have asked me for an old valve. I did not throw away my valves when I stopped using them. They are stowed under the house, out of the way and almost forgotten. I still have some 6J8s, 6U7s, 6B8s, 6V6s, and 5Y3s. Can anyone remember what they were used in'? 90 SILI CON CI-111' ed. These chips take up a lot of space, consume power, require larger circuit boards and occasionally are not fast enough. All those problems can be overcome by using a programmable logic array (PLA). A PLA is an LSI or VLSI circuit consisting of multiple gates and inverters arranged on a chip in such a way that they may be randomly connected to perform almost any logic function. Semiconductor technology now permits manufacturers to quickly, easily and inexpensively manufacture custom circuits using PLAs. Other PLAs are field programmable. That is, the designer may specify his own circuit, then implement it himself with a PLA. Such circuits make it possible to replace MSI functional combinational circuits and all And another query: the twin triodes in the 6ES8 were described as being run in "cascade", meaning one under the other, like a waterfall. In my dictionary, a waterfall is described as a cascade. I have never found anyone who can explain why an electronic cascade is spelled "cascade" . Do you know'? Thank you J.L., for that little piece of nostalgia. I can't offer any explanation as the origin of the word "cascade", but I doubt whether it has any particular linguistic significance. I imagine it was nothing more than a sudden inspiration by someone groping for a term to describe the new circuit concept. Regarding the supply of power to the old MHAs. I cannot recall any systems where 240V was run up the mast, and it would have been a rather complex and expensive setup. As I recall, the most popular arrangement used the feeder as a supply line, power being fed up it at some convenient low voltage typically 32V if I remember correctly - to a transformer in the amplifier which supplied the required voltages. As to whether anyone can remember the valve types you mention: yep, I sure can; they are part of our history! ~ Fig.25: PLAs are programmed by means of fusible links in the integrated circuit chip. 1 I . 0 f1~~i 4) C I) 4) l 4, of the random gates and inverters normally required to implement a special function. In some cases, the entire circuit can be reduced to a single PLA chip. A general block diagram of one type of PLA is shown in Fig.24. The circuit has multiple inputs with inverters and buffers to supply normal and complement signals. Those lines can be interconnected with any one or more of the inputs to the many AND gates on the chip. The AND gate outputs are, in turn, connected to the OR gates as shown. The circuit outputs appear at the OR gates or the associated inverters. Most practical circuits have many more input and output lines than shown. A typical circuit might have eight inputs and eight outputs. The interconnection of the various signals on the chip take place in a variety of ways. One common way is to use fusible links as shown in Fig.25. Each AND gate input is connected to all input lines with a tiny tungsten fuse when the circuit is manufactured. Then the chip can be " programmed" by passing a high current through the appropriate chip pins. The high current will open the fusible links where no connection is desired. In that way, the circuit can be customised to the application which is why PLAs are so popular. Reproduced from HANDS-ON ELECTRONICS by arrangement. Copyright (c) Gernsback Publications, USA. ~ SHORT QUIZ 6: COMBINATIONAL LOGIC CIRCUITS 1 . Combinational circuits may contain flipflops. a. True b. False counter is incremented by the clock , the output is observed . Which of the following functions is baing carried out: a. Decoding c. Binary addition b. Demultiplexing d. Parallel-serial conversion 2. Identify the logic circuits shown in the figure below by filling in the correct names : :=G-c ~ (a) (b) e-Q- ~ 7. Parity is a scheme tor _ _ _ _ _ _ __ 8. Give the parity bit tor each word below: a. 10010010 Odd parity= _ _ _ __ b. 10111101 Even parity = _ __ _ _ (d) (c) 9. Add the following binary numbers: a. 1001 b. 10011110 0111 b. 111 10101 a. b. c. 10 . The following is the truth table of which circuit? d. 3 . Draw a decoder circuit that outputs a binary 0 when it recognises the binary number 10111101 . 4 . A 3-line to 8-line decoder is sometimes called a(n) _ __ __ _ _ _ _ __ __ __ _ _ 6 . Three flipflops of a binary counter are connected to the A, B and C inputs of the 1-of-8 multiplexer shown in Fig .11 . A data byte (8-bit word) is applied to the D0-D7 inputs. As the I J '\.. I I I ~o ( AB11B 0!601 aIqBWWB1601d t!ONX ·q t!OX P (sov) ~ ~oo ~oo ~ ~ ·q (9 ~) 000 ~ ' B Q = Aj!JBd ua113 - ~0~~~~0~ 0 = Al!JBd PPO ·o WO WO~ ·-e UO!P9l9P 10113 C 0 1 1 0 1 0 a. OR b. XNOR c. OR d. XOR 12 . An LSI/VLSI circuit that can be customised to eliminate combinational circuits made with SSI and MSI circuits is called a _ _ _ _ __ _ _ ANSWERS TO QUIZ r-4---o 8 11 . A single-bit comparator is called a: a. AND c. OR b. XNOR d. XOR 5. Another name tor the data selector is _ _ _ I A 0 0 1 .G ~ .~ ~ ·o~ 6 ·q ·g .L ·1nd1no a41 lB AIIB!\Uanbas 1-eaddB Oj SjndU! BlBP a41 Bu,snB::> '19ljj0UB 1au-e auo paIq-eua a1B sa1-e6 1axaId111nw a41 'pa1uawa1::>uI S! 1a1unoo a41 sv ·uo,s1a11uoo I-epas-01-Ia11-e1-ed ·p ·g 1axaId!\lnll'J ·g IB\00 ·v 146p lB 6U!MB1P aas '£ t!O ·p '. 19j1911U! ·o '. ONVN ·q '. tfOX 'B ·c ·s1a11a11u, PUB sa1-e6 AIUO asn s1,n::>l!O IBUO!lBU!qW08 ·asI-e.:1 ·q · l A l'lllL '1988 91