Fullscreen HTML5Med Res (??MB)HTML4

' ' 1f1-'l There are two basic types of digital logic circuits, combinational and sequential. Combined circuits are made up of logic gates connected in a variety of configurations. Combinational circuits typically have multiple inputs and outputs. Their outputs are a function of the input states, the types of gates used, and how they are interconnected. Sequential logic circuits also contain gates, but their main element is a logic circuit we have not yet discussed; it's called the flipflop. A flipflop is a circuit used for storing one bit of data. Because flipflops are a kind of memory circuit, they permit a variety of storage and timing operations to be performed. Some of those operations include counting, shifting, sequencing and delay generation. In this lesson, you are going to learn about the various types of flipflops and how they are used. In a future lesson, we will cover more advanced sequential logic circuits, including counters and shift registers. Note: in the following discussion, we use the expression "high" to refer to a binary 1 logic level or some positive voltage in the + 3V to + 5V range. "Low" is used to designate a binary 0 logic level, which is ground or Oto + 0.2V. Data latches The simplest form of flipflop is the latch or RS flipflop. Like all other flipflops, this type is capable of storing one bit of data. It has two inputs and two outputs, and is usually represented by the simple logic block shown in Fig.1. For example: to store a binary 1, you apply a signal momentarily to the set input. To store a binary 0 in the latch, you momentarily apply a logic signal to the reset input. Once the latch is set or reset by the input pulse, it remains in that state. The flipflop remembers which state it was set to (0 or 1) until the state is changed, or until power to the circuit is removed. To determine which bit is stored in the latch, you look at the outputs. By examining the normal output with a voltmeter, logic probe or oscilloscope you can determine which state the flipflop is in. If the normal output is binary 1, then the flipflop is set and storing binary 1. If the normal output is binary 0, the flipflop is reset and binary 0 is being stored. The complementary output is an inverted version of the normal output and is useful when the latch is used to drive other logic circuits. Incidentally, you will note that in Fig.1 the outputs of a flipflop are normally labelled with letters of the alphabet. Q is commonly used with flipflops, but other letters of the alphabet or other multi-letter combinations can be used too. Also, when a line or a bar appears over a letter as in Q, that signal is the reverse of its counterpart, Q. That is to say, if Q is low, then Q (Qbar) will be high and vice versa. A latch or RS flipflop is easily constructed with NAND gates as shown in Fig.2. The gates are conINPUTS OUTPUTS SET~NORMAL RESET--l_r-coMPLEMENT Fig.1: the logic symbol for an RS (reset-set) flipflop. Note the complementary outputs (Q and Q-bar). 1-"EBRUARY 1988 85 nected with the output of each connected to the input of the other. The operation of a latch is easy to understand if you remember how a NAND gate works. The simple truth table in Fig.2 will refresh your memory. TRUTH TABLE OF NANO GATE INPUTS A D 1 1 1 D 1 0 0 Q Fig.2: an RS flipflop constructed of NAND gates. When power is first applied to a flipflop circuit, it comes up in one of its two stable states. Because of minor differences between the two gates, the circuit will flip to either the set or reset state immediately upon power-up. It is not possible to predict which state will occur. Let's assume that the flipflop initially comes up in its set state. That means that the Q output is binary 1. This binary 1 also appears at the input of gate 2 together with the reset input. The reset input is shown open here and this has the same effect as a binary 1 input. With those conditions on gate 2, its output will be a binary 0. The output of gate 2 is applied back to the input of gate 1. The set input is open and has the effect of a binary 1. However, it has no effect on the circuit, because the binary 0 input to gate 1 causes its output to remain high. Just to be sure you understand the idea, trace the circuit state by assuming the flipflop comes up in the reset condition. Start out with the Q-bar output being binary 1 and repeat the above analysis. Keep in mind that the set and reset inputs will not normally be open. Instead, they will be held at binary 1 level. To change the state of the flipflop, either the set or reset input must be pulled momentarily to the binary O level. Assume that the flipflop is initially set with the Q output being binary 1. If we want to reset the latch, we simply apply a brief pulse that switches from binary 1 to binary 0 and back again. The•binary 0 input on gate 2 immediately forces its output high. That high output to the input of gate 1 along with the high set input causes the Q output to go low. The flipflop thus changes state from set to reset. Incidentally, if another reset pulse is applied to the reset input, no additional change of state will occur. Similarly, if the flipflop is already set, additional set pulses will have no effect on the circuit. u--~___.r 1 C D 1 D 1 I I RESET:---,---~ OUT , B D D 1 1 1 SET 0 AMBIGUOUS STATE'_/ Fig.4: input and output waveforms for a latch. show all possible states of a latch. The truth table in Fig.3 shows the various combinations of inputs and outputs. We should explain that there are two special input conditions. When both inputs are binary 1, the state of the latch is not affected. Since we don't know which state the latch is in, we simply designate the output with the letter X - which, of course, can represent 1 or 0. Another special condition occurs when both inputs are binary 0. That will force both outputs to the binary 1 level. Looking at the Q output, you will see a binary 1 output and, therefore, would suppose that the the flipflop is set. However, that is not the case because the Q-bar output is also a binary 1, implying that reset is an ambiguous state that does not represent either the set or reset condition. It should be avoided by eliminating the possibility that both inputs could go to binary 0 simultaneously. The operation of the latch can also be illustrated with input and output waveforms as shown in Fig.4. Take a minute to look over those signals to be sure you understand the operation of a flipflop. The way to do it is simply to observe the Q output to determine the state of the flipflop. Note how the set and reset inputs change it. The Q-bar output, of course, is simply an inversion of the Q output except in the ambiguous state. You can also construct a latch using NOR rather than NAND gates. A NOR latch is shown in Fig.5. The flipflop has normal and complement outputs, but note that the positions of the set and reset inputs have been reversed. Because the operation of a NOR gate is different to that of a NAND gate, the signals used to change the state of the flipflop must be binary 1 rather than binary 0, as with NAND gates. To tell the truth Fig.5: RS flipflop constructed of N OR gates. As with logic gates, a truth table can be used to IT INPUTS OUTPUTS II S R 0 0 0 1 0 1 1 0 0 1 X 1 1 Fig.3: the truth table for an RS flipflop. 86 SILICON CHIP u 1 INPUTS ij I SET RESET 1• . D D D 1 1 1 i X = EITHER D DR 1 • = AMBIGUOUS STATE Fig.6: truth table for a NOR latch. D 1 D 1 OUTPUTS 0 ij X D X 1 D 1 D o· X = EITHER D DR 1 • = AMBIGUOUS STATE , SET 0 , nJ1 I 0:J I ~1I I I I I I RESET 0 I ,I 0 I L I I I i n AMBIGUOUS S ! A T E ~ Fig.7: timing waveforms for a NOR latch. Normally, both the set and reset inputs will be binary 0. At that time, the flipflop will either be in its set or reset state. To change the state of the flipflop, a momentary binary 1 pulse is applied to either the set or reset input. Fig.6 shows the truth tble for a NOR latch. The operation of that circuit is further described by the timing waveforms shown in Fig.7. clearly defined logic levels are created by that simple circuit, the problem lies in the garbage generated by the switch in the brief time while it being is opened or closed. The waveforms of Fig.8 illustrate that effect. Fig.9 shows a latch debounce circuit. A singlepole, double-throw (SPDT) switch must be used in this application. While the contacts still bounce at the inputs to the latch, they have no affect on the output. Recall that if a signal is repeatedly applied to the set or reset input, the flipflop will not change. The result is an output signal that follows the switch conditions, but whose transitions from Oto 1 to Oare clean. A NOR latch can also be used for switch debouncing, as shown in Fig.10. However, note that the switch input is + 5V, or a binary 1, rather than ground (binary 0) as in the NAND latch. Apart from that, the operation of the circuit is similar. .,. +5V . Debounce A popular application for a latch is switch debouncing. Whenever two metal contacts are opened or closed, they will often vibrate or not cleanly make contact for a short duration. Any dirt or other foreign matter on the contacts will aggravate the problem. The result is multiple pulses or spikes during opening or closing. Such noise can falsely trigger logic circuits. A typical arrangement is shown in Fig.8. With the switch open, the output is a binary 1 level, as seen through the resistor. When the switch is closed, the output is brought to ground or binary 0. While clean, CONTACT BOUNCE NOISE SWITCHOPEN(+5V) ~ / ~ t Fig.10: a NOR latch used for switch de bouncing . Clocked RS flipflop The latch or RS flipflop is an asynchronous sequential circuit. That means that the output changes state immediately upon application of the input signals. On the other hand, some logic circuits act in response to a master timing signal called a clock. A clock is an oscillator circuit that generates a fixed-frequency periodic sequence of pulses that are used to control all timing and sequencing operations in a digital circuit. Logic circuits controlled by a clock are referred to as synchronous because all changes of state are initiated and occur in step with the clock signals. Clocked logic circuits are more predictable and are generally immune to "race" conditions that exist in some ,,T oi------ Fig.11: a clockdriven RS flipflop. SWITCH CLOSED (OV) Fig.8: waveform for undesired switch-contact bounce , SET 0 +5V RESET ~~, I OL~ I..---_ a o- - - - ---, I CLOCK +5V Fig.9: a NAND latch used for switch debouncing. 0 Fig.12: timing waveforms for a clocked latch. FEBRUARY1988 87 OATAINPUT=O=Q CLOCK CK Q Fig.13: logic symbol for a D-type flipflop D CK Q 0 0 0 1 0 1 X 0 X 1 1 1 1 D 0 III 1 CK Fig.15: truth table for a D-type flipflop. 0 I Fig.16: timing waveforms for a D-type flipflop. Fig.14: a D-type flipflop made from a quad 2input NAND integrated circuit chip. asynchronous circuits. A basic latch can be used synchronously, as shown in Fig.11. Here the set and reset inputs are buffered by NAND gates. The operation of those NAND gates is controlled by the clock. It is assumed that the latch is a NAND flipflop with set and reset inputs which must momentarily be switched to the binary O condition to cause a change of state. To set the latch, a binary 1 is applied to the set input and a binary O is applied to the reset input. With those inputs, the latch does not change state immediately. The reason for this is that the clock is normally in the low position. That inhibits the NAND gates, keeping their outputs high and the latch unaffected. When a binary 1 clock pulse occurs, the NAND gates are enabled and the set and reset input signals are applied to the S and R inputs of the latch. The S input goes low while the R input remains high. The result is that the latch is set and the Q output goes to binary 1. To reset the latch, the reset input is made binary 1 and the set input is made binary O. When a binary 1 clock pulse occurs, the latch changes states. This form of synchronous operation is better illustrated with timing diagrams as shown in Fig.12. Various input and output conditions are illustrated. Note that the actual change of state occurs on the positive-going or O to 1 transition of the first clock pulse following an input-state change. input is required to initiate the change of state. Note that when the clock is 0, the flipflop simply remains in the state to which it changed on a previous clock pulse. When the clock pulse is binary 1, the latch stores the input state. If the input is binary 1 while the clock is high, the latch will set and its output will be binary 1. If the input is binary O while the clock is high, the latch will reset and the normal output will be binary 0. Keep in mind that while the clock input is high, the normal output directly follows the signal applied to the D input. Ordinarily the clock only occurs for a very short interval. Because of the input gating circuits, ambiguous states cannot occur in D-type flipflops. The waveforms in Fig.16 summarise the operation of the D-type flipflop. All possible combinations of inputs and outputs shown in the truth table are repeated in the timing diagrams. Take a look through them to confirm your knowledge of the circuit's operation. Storage registers One of the main uses for D-type flipflops is to form storage registers. A storage register is a circuit capable of storing a binary word. One flipflop is need+5V0---+------+------<1---- D-type flipflop The D-type flipflop is a variation of the gated latch and it is a synchronous circuit in that it uses a clock signal to control the setting and resetting operations. The main difference between the D-type flipflop and the gated latch is that the D-type circuit has a single input, as shown in Fig.13. To set the flipflop, a binary 0 is applied to the data input. The flipflop transfers the input value to its output when a clock pulse occurs. Fig.14 shows a D-type flipflop with NAND gates. With that arrangement, a D-type flipflop can be quickly constructed out of a standard quad 2-input NAND gate. However, that is not usually necessary as ICs containing 2, 4 or 8 D-type flipflops are readily available. The truth table in Fig.15 illustrates D-type flipflop operation. Here we are assuming that a binary 1 clock 88 SILICON CHIP r· ------- ------- ------- --- - , O I SWITCH I REGISTER I O I I I I _ I I . I ----- ------ ----- +5V0-------------4>----___, Fig.17: a 4-bit storage register. ___ J ed for each bit in the word. For example, to store one byte of data, eight flipflops are needed. Fig.17 shows a storage register for a 4-bit word. The parallel inputs to the register are supplied by a set of switches referred to as a switch register. The switch register allows you to manually select a binary word to be stored in the register. The output of the register drives light-emitting diode (LED) driver circuits, to indicate the flipflop states. Note that flipflop A is designated as the most significant bit (MSB), while flipflop D is the least significant bit (LSB). Therefore, in Fig.17, the word stored is 1010. JK flipflops The most versatile form of storage circuit is the JK flipflop. It can perform the functions of both RS and Dtype flipflops but also has its own unique features. The JK flipflop is widely used to form storage registers but finds its greatest application in sequential logic circuits such as counters and registers. You will learn more about these circuits in a future lesson. The symbol used to represent a JK flipflop is shown in Fig.18. We won't discuss the internal logic circuits of a JK flipflop because they are somewhat complex. Besides, you don't really need to know what's inside to understand its operation or to use it. The JK flipflop has five inputs and two outputs. The S and C inputs, meaning "set" and "clear", are similar in operation to the set and reset inputs on a basic latch. The J and K inputs are synchronous inputs similar to the set and reset inputs on a gated latch. "J" means set while "K" means reset. The T input is for the clock. Finally, standard normal (Q) and complement (Q-bar) outputs are generally provided. The S and C inputs are asynchronous in nature. Those inputs are normally held high and in that state have no affect on the operation of the flipflop. However, to set or reset the flipflop as you would an ordinary latch, momentary low signals are applied as needed. For example, to reset the flipflop, a binary 0 pulse would be applied to the C input. The normal output would then go to the binary O state. The truth table in Fig.19 illustrates the effect that the S and C inputs have on the outputs. The results are identical to those obtained with the NAND latch discussed earlier. It is necessary to avoid the condiSET SET Fig.18: logic symbol for a JK flipflop. NORMAL CLOCK--T RESET COMPLEMENT CLEAR Fig.19: truth table for the S and C inputs of a JK flipflop. INPUTS OUTPUTS s C Q Q 0 0 1 1 0 1 D 1 1 0 X 1• 1 0 1 x X = EITHER 1 OR 0 • = AMBIGUOUS STATE AB (a) (b) Fig.20: clock pulses showing negative (a) and positive (h) edge triggering. tion where both Sand C inputs are low, so that the ambiguous state can be avoided. The asynchronous S and C inputs override the J, K and T synchronous inputs and their effect is immediate. The main application for the S and C inputs is presetting. To preset a flipflop means to put it into one state or another prior to another operation taking place. An example is the resetting of a storage register. Resetting or clearing a register means setting all the flipflops to the binary O state. That can be done by connecting all the C inputs of the flipflops together and applying a low pulse. The register is then said to be cleared. Presetting can also mean setting the flipflop. Occasionally it is necessary to load a specific binary number into a register prior to another operation beginning. By the use of external gates connected to the S and C inputs, any binary number can be preloaded into the register. Now let's consider the synchronous inputs. As in a gated latch, the J and K inputs are used to set and reset the flipflop but under the control of a clock pulse. If the J input is made binary 1 and the K input binary 0, the flipflop will be set when the clock pulse occurs. If the J input is a binary O and the K input is a binary 1, the flipflop is reset on the occurrence of the clock pulse. In most JK flipflops, that change of state occurs on the trailing or negative edge of the clock signal, as illustrated in Fig.20a. Some flipflops initiate a set or reset operation on the positive or leading edge of the clock signal as shown in Fig.20b. Negative edge triggering, however, is more common. When both the J and K inputs are held at binary 0, nothing happens. Even when a clock pulse occurs, no change of state occurs. The flipflop simply remains in the state in which it was previously set. When both the J and K inputs are binary 1, an unusual action occurs. When a clock pulse appears, the flipflop will be toggled or complemented. What that means is that on the trailing edge of the clock pulse, the flipflop will simply change state. That unique feature of the JK flipflop allows it to be used in a variety of counter and frequency divider circuits as you will see. Fig.21 illustrates the toggling or complementing mode of operation. Synchronous operation of the JK flipflop is summarised by the truth table in Fig.22 which shows the four possible combinations of the JK inputs. Note that the output is expressed in two ways. First, the Qn column is the normal output state of the FEBRUARY1988 89 f--:- CLOCK PERIOD M 1 CLOCK 0 1 0 CLOCK (T) 01---' I OUTPUT PERIOD • 0 I 1---...; Q Fig.21: the toggling or complementing of a JK flipflop by a clock when the JK inputs equal 1. I• INPUTS J K 0 0 0 1 1 1 D 1 0 Fig.23: synchronous timing waveforms of a JK flipflop. OUTPUTS On On+1 X X X 0 1 X X X 3.2MHz Fig.22: truth table showing synchronous operation of a JK flipflop. 6.4MHz CLOCK INPUT X=EITHEROOR1 flipflop. All entries in that column are designated X which means that the flipflop may be either set or reset. The other output column is designated Qn + 1 . That is also the normal output, but it designates the state of the flipflop after the occurrence of a clock pulse with the designated JK inputs. Fig.23 shows the timing waveforms of a JK flipflop. Work your way through those diagrams from left to right to be sure that you understand all conditions trailing edge triggering is assumed. Frequency dividers As indicated earlier, the JK flipflop finds its greatest use in various kinds of registers and counters. We won't discuss those here as a complete lesson is devoted to them later. However, we do want to illustrate several simple applications. A major JK flipflop application is in frequency A.C.E. R s NOTE: ALL JK INPUTS = 1 Fig.24: cascading JK flipflops to form a frequency divider. dividers. Refer to the input and output signals of a typical JK flipflop as shown previously in Fig.21. Note that each time a negative-going transition occurs, the flipflop will toggle. Because of that, the output of the flipflop is one half the frequency of the input. We say that the flipflop is a divide-by-2 circuit. If a 100Hz input signal is applied to the flipflop, the output will be a 50Hz signal. JK flipflops can be cascaded to perform frequency division by multiples of 2 (4, 8, 16, 32 etc). In Fig.24 we show four JK flipflops cascaded with the normal output of one connected to the T input of the next. Naturally, each flipflop divides by 2. With the 6.4MHz ESTABLISHED OVER THIRTY YEARS 1 0B/3 Kenneth Road, Manly Vale 2093. Telephone (02) 949 4871. cn microbee 0/1/)computer COMPUTERS & COMPONENTS Reconditioned "pre-loved" Microbee 32K personal computers. These units are in good condition, requiring only a suitable 12V DC power supply and interface cable to put it to work on your VDU. 1 1r·i·•:,~1-'.ttta A genuine bargain at only $210.00 . P&P NSW $4.30; interstate $6.50. The Compack Printer Stacker - dispenses your printer paper, eliminates cluttered table tops. Will support a 30kg printer. Tray capacity 500 cont. sheets (8.5 x 11 in). Price $30.60. P&P $3.50. SILICON CHIP 400kHz BOOkHz ELECTRONICS CENTRE The solution to paper & printer problems! 90 . 1.6MHz 12V DC 1 amp power supply - $15.95. P&P NSW $3 .50; interstate $5.00. New PC Boards MB8431 Anti Glitch Card ........ $3.50 MB8346 Viatel Card ............ ......... $3.50 Give your floppies a safe home DX-100B diskette file - stores 100 5.25in floppies; lockable (2 keys supplied). Special price to SILICON CHIP readers: only $26.50. P&P $2.00. We also have a 3.5in version that holds 90 disks. Price $18.95 plus $2.00 P&P. These p1 ices can 't last so get in quickly. +5V I II III II II I I II I I I II I I II I 112•74LS113 14 I I IIIIIII I III 11 I 1 1 - 1k 10k 1 _____, ~---'-------'---'---'I 1 -'--J.. 1 1 1 1 1 1 I I I I I 1 I r L Fig.25: output waveforms from a 4-stage frequency divider. Negative edge triggering is used. input shown , the flipfl op outputs are 3.2MHz. 1.6MHz, 800kHz and 400kHz. The wa veforms of Fig.25 show th e full operation of the circuit. The division fa ctor for a given number of flipflops is shown by the equation below. F represents the frequency division rati o whi ch is equal to 2 raised to the power n, whe re n is the number of flipflops in the c hain . With four flipfl ops. the frequ ency ra tio is : F = 2 11 = 2 4 Learn by building Fig.26 shows a simple circuit you can build to unde rstand the opera tion of a JK flipflop. Here a 555 time r IC is connected as a clock. It generates a clock signal that will r epea tedly toggle the JK flipflop whenever the pushbutton switch is depressed. When the switch is r eleased, the JK inputs a re held low a nd .,. > NORMALLY CLOSED PUSH BUTTON SWITCH Fig.26: a coin flipflop simulator illustrating the operation of a JK flipflop. the clock has no effect on the flipflop. The outputs of the JK flipflop are connected to LED driver circuits. You will find that the outputs will always be complementary, with one LED on while the other is off. The circuit simulates the flipping of a coin. For example, heads might represent set while tails indicates reset. To flip the coin, all you do is press the pushbutton switch. The JK inputs go high. The flipflop will then toggle repeatedly for a period of time. When you release the pushbutton, the JK inputs go low. The flipflop will then be set or reset depending upon where the flipflop was just prior to releasing the switch. Because of the high-speed nature of the clock, and the random depressing and releasing of the pushbutton, the circuit accurately simulates the random flipping of a coin. Reproduced from Hands-On Electronics by arrangement. Gernsback Publications, USA . it © SHORT QUIZ ON LESSON 4: UNDERSTANDING FLIPFLOPS 1 . When a flipflop is storing a binary 1 , it is said to be: b. set a. reset 2. Another name for a latch is_ _ _ _ _ _ __ 3. A common application of a latch is,_ _ _ __ 4 . To clear a flipflop means to: a. reset it to O b. preset it to 1 5. Flipflops such as the D and JK types which change state on the occurrence of a clock pulse are said to be _ _ _ _ _ _ _ _ _ _ _ _ __ 9. A 6-bit register is made up of 0-type flipflops. The flipflops are labelled A to F with A being the LSB and F being the MSB. The flipflop outputs are A =low , B = high, C = high, D = low, E = high , F = high , where high = 1 and low = 0 . The decimal equivalent of the binary number stored in the register is_ _ _ _ _ _ _ _ __ 1 0 . A frequency divider made up of seven cascaded JK flipflops generates an output frequency of_ __ ,kHz from an input of 51 2kHz ANSWERS TO QU IZ 6 . When the JK inputs are O and a clock pulse occurs, the flipflop will: a. set b. reset c. tog£)1e d. not change state 7. When the JK inputs are 1 and the clock pulse occurs, the flipflop will : b . reset a. set d. remain in the same c. complement state 8. The clock input to a D flipflop is high . The D input is low. The complement output will be_ __ (ZH)1J7 = LG + ZH)1"?, ~9) ZH)1J7 ·o ~ (v9 = o~~o~~ = 'v'B:Jm.::1l t9 ·5 ·peJJeAUI eq ll!M 1nd1no 1uewe1dwoo e41 ·1ndu1 a e41 se ewes e41 eq IIIM 1nd1no 1ewJou e41'46141ndu1 )100!0 941411M ·4614 ·g e16601 JO 1uewe1dwoo ·p ·z e1e1s e6ue40 1ou ·p ·g SllOUOJ40UAS . 9 o 01 11 1eseJ ·e ·v 5upunoqep 1oe1uoo JO 4011Ms ·s dOIJdllJ S8 ·c ies ·q · ~ FEBR UARY1988 91