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' ~ -·T-1 I • , t ' ·.$ . -:: +~::• ., ' ¥••--ey a• ~ . •• • •Y•~==•~-Y'') ? I ' . l ··-·· }'-··. » ••\•• ! Having looked at the va:ri<>~s :type$ of Jlipf\ops, ~~,r~.}}O'r -~ ea~I,~O-!~okjhto, s':s~e~tia['~~ic •·J ,· J ... "'·' t· · . j _cq-.~~~s~ '1E;I"e ·-w~ -~~s~~;i:yer !!ow ~!!J:~I'Y c;ou,1:1.~ersT,,: and shift registers worlc~ · · · · · . ' . · - .. ;l=t . ,. 0 ""'· . b. i_~ t4,~; 'i:, 1 - ! ,. ' ~ -1· ~ «-. 'Q&, ,. LESSON 5: COUNTERS & SHIFT REGISTERS ,,· >··· By Louis E. Frenzel, Jr. · · ··--~~nt· ® '$, :< f The two basic types of logic circuits are combinational circuits and sequential circuits. Combinational circuits are made up of logic gates connected in a special way. The outputs are a function of the inputs and how the gates are interconnected. Sequential circuits are made up of both gates and flipflops. The flipflops are the primary components as they are used to store binary states. Those states can be changed by input signals to form new states. Sequential logic circuits are designed to perform a variety of storage and timing operations. A sequential logic circuit can retain a binary word or manipulate it in various ways. Sequential circuits can also perform many different kinds of timing and sequencing operations. The two most commonly used sequential logic circuits are counters and shift registers. Virtually every digital circuit contains a counter or a shift register of some type. Binary Counters A binary counter is a series of JK flipflops which counts the number of input pulses that appear at the PARALLEL COUNTER OUTPUT A(LSB) COUNT 8 J --~·r IN K T c K ii RESET OR CLEAR Fig. 1: a 4-bit binary counter. All J and K flipflops are connected to binary 1 (high). Each flipflop toggles on the trailing edge of a clock waveform applied to input T. ' ! ' t input to the first flipflop. The counter stores the sum of input pulses as a binary number. To determine the number of input pulses applied to the counter, you simply look at the flipflop outputs and read the binary number stored there. Many digital circuits require that you keep track of the number of pulses that occur at a given point in the circuit. A counter is used for this purpose. Fig.1 shows a logic diagram of a simple 4-bit binary counter with the JK flipflop outputs designated as A, B, C and D. Each flipflop output is connected to the clock or toggle (T) input of the next flipflop in the series. This is referred to as cascading. The pulses to be counted are applied to the toggle input of flipflop A. All J and K inputs are assumed to be at binary 1 (high). Another important connection shown in Fig.1 is that all the clear (C) or reset inputs to the JK flipflops are connected together to form a common reset line. A binary O applied to the reset line will clear the flipflops so that the binary number stored in the counter is zero (0000). We can read off the binary number stored in the counter by looking at the logic states of the normal flipflop outputs. These are read from right to left, or DCBA. The A bit is the LSB (least significant bit) and the D bit is the MSB (most significant bit). Now let's see how the counter operates. Assume that we are using JK flipflops that change state when the clock input switches from 1 to 0. We call this the trailing edge or the negative-going transition of the input pulse. Now assume that an input pulse occurs that switches from high to low. This causes flipflop A to toggle from the binary Oto the binary 1 state. Looking at the flipflop outputs and reading them in the DCBA order, we see that the binary number stored in the MARCH 1988 81 NUMBER OF INPUT PULSES 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 C B A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 0 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Fig.2: truth table for a 4-bit binary counter. counter is 0001. This is the binary reading for the decimal number 1. So one input pulse has occurred. When the second input pulse occurs, flipflop A is toggled again. This time it switches from the 1 to 0 state. As its state changes, the A output switches from high to low. That in turn causes flipflop B to toggle and set, its normal output going from O to 1. The transition appears at the clock input to the C flipflop, but the flipflop ignores low to high transitions. If we now look at the counter outputs, we see that the number stored there is 0010 or the binary equivalent of decimal 2. Two input pulses have now occurred. If you continue to apply input pulses to the counter, one flipflop will simply toggle the next in sequence and the binary number stored in the counter will increase by one for each input pulse that occurs. When this happens, we say that the counter is being incremented. The counter counts up from O to the maximum value that the counter is capable of holding. Fig.2 shows the truth table of the 4-bit binary counter. Note that the decimal number of input pulses applied to the counter corresponds to the binary value displayed by the outputs. This is true only if the counter has been reset prior to counting. An important point to note is that when fifteen input pulses have occurred, the binary number stored is 1111. When the 16th input pulse occurs, flipflop A toggles to 0. This in turn toggles B to 0, which in turn toggles C to 0, which toggles D to 0. The binary number PULSES TO BE COUNTED 1I 2I 3I 4 I 5I 6 I 7I 8 II 9 10I 11l 12I 13l 14I 15I A I 1 C 0 0 0 I I I--- 1 1 1 1 1 1 I o 0 0 1 ...o_"-o_...o_o=----=-o__,o..._..::.o__,o'-'! 1 1 1 Fig.3: input and output waveforms for a 4-bit binary counter. 82 SILICON CHIP 0 1 ~ I I 0 1 1 1 1 1 ·now indicated in the counter is 0000. This is equivalent to the initial reset state described earlier. In other words, the number 16 is too large for the counter to store. So once a 4-bit counter counts to 15, the next input pulse simply returns it to zero and it starts again. Fig.3 shows the input and output waveforms for the 4-bit binary counter as 16 input pulses are applied. Those timing waveforms illustrate all possible states of the counter. You may want to trace through the logic diagram of the counter and correlate each of the pulses shown in the timing diagram with each flipflop. This will ensure that you understand how each flipflop changes state on the high-to-low transition of each input pulse. Counting to Higher Values To count to larger numbers, all you do is add more flipflops to the counting chain. Each additional flipflop lengthens the binary word of the counter by one bit, thereby doubling its maximum count capability. The total number of states that a counter can assume is 2N where N is the number of flipflops. With four flipflops, the total number of states is 24 = 2 x 2 x 2 x 2 = 16. Those states are O (0000) through 15 (1111). You can determine the maximum count capability of the counter with the simple formula shown below: M = 2N - 1 where M = maximum count number and N = number of flipflops. With four flipflops, the maximum count capability is: M = 24 - 1 = 15 A 5-bit counter has a maximum count capability of 31. A 6-bit counter can count to 63, a 7-bit counter to 127, an 8-bit counter to 255, a 12-bit counter to 4095 and so on. ' A binary counter can also be used as a frequency divider. Take a look at the waveforms shown in Fig.3. Recall that a JK flipflop acts as a divide-by-2 circuit. As you can see in Fig.3, the output of the first flipflop has a period that is twice the period of the input pulses being counted. This means that the output of flipflop A is half that of the input frequency. Now look at the output of flipflop B. Again, you can see that its frequency is half that of flipflop A's output. A similar relationship exists in the remaining waveforms. The output frequency of flipflop B is onefourth that of the input to flipflop A. The outputs of flipflops C and D are one-eighth and one-sixteenth of the input frequency respectively. The frequency division factor of a binary counter is simply 2. With four flipflops, the frequency division factor is 16. A binary counter with eight flipflops will divide an input frequency by: 28 = 2 X 2 X 2 X 2 X 2 X 2 X 2 X 2 = 256 Thus, if a 6.4MHz input signal is applied to the 4-bit binary counter, the output of flipflop D will be 6.4 16 = 0.4MHz or 400kHz. Preset Counters The term preset means to put a flipflop into one state or the other prior to another operation taking Fig.6: count sequence of a 4-bit down counter. INPUT PULSE 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 2 3 COUNT .4 IN K C 5 6 7 8 ii 9 10 11 12 13 14 15 Fig.4: flipflop preset circuitry. place. Presetting a counter simply 1!1eans load~ng a binary number into the counter pnor to the mput pulses being applied. In many applicat~ons, the preset can simply be a clear or reset operation. If this was not done, the binary numbers stored in the co~nter would have no meaning unless you knew the bmary number stored in the counter beforehand. It's not too hard to see that it's a lot simpler to clear the counter first so that the binary number stored in the counter exactly represents the number of input pulses that occurred. On the other hand, there are applications where it is desirable to begin counting at some predetermined number. This is done with preset circuitry that takes advantage of the asynchronous set (S) and clear (C) inputs of the JK flipflops. A typical circuit for one flipflop is shown in Fig.4. If you would like to preset the flipflop to binary 1, you apply a binary 1 to the preset input _at gate fi-:-· Then you apply a binary 1 to the LOAD mput. This forces the output of gate A low and the output of gate B high, The result is that the asynchronous set input of the flipflop causes it to store a binary 1. Applying a binary O to the preset input and then switching LOAD from low to high will cause the flipflop to be reset or store a binary 0. . When all flipflops in the counter have the preset circuitry shown, then a parallel binary number can be applied to the counter and loaded into it prior to beginning the count operation. To show how that presetting works, assume that the 4-bit binary counter described previously has preset circuitry. Suppose that we apply the binary number 1010 to the preset inputs and load it into the counter. The counter outputs DCBA will read 1010 (decimal 10). Then assume that input pulses occur. If four input pulses occur, the counter is incremented to 1110 (ie, to decimal 14). Down Counters The binary counter described previously is an up counter as each input pulse increments the binary IN Fig.5: a 4-bit binary down counter. OUTPUTS C B 0 1 1 1 1 0 1 1 1 1 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 0 0 0 0 0 A 1 1 0 1 1 0 0 0 1 1 1 0 1 0 0 0 INPUT PULSES A B 1 C 1 1 Io 0 0 o I Io 1 I 0 0 I I 0 1 1 1 Io 01 0 0 0 0 0 0 01 Fig.7: input and output waveforms for a 4-bit down counter. number stored in the flipflop. That is, as each input pulse occurs, one is added to the count. It is also possible to construct a down counter so that the binary number in the counter is decremented by one as each input pulse occurs. As a result, down counters count backwards. For example, if a 4-bit binary down counter were preset to 1111, sequential input pulses would decrement it to 1110, 1101, 1100, etc. Some digital applications require this capability. Fig.5 shows how to connect four JK flipflops to form a down counter. Again the flipflops are cascaded by connecting the output of one flipflop to the clock (T) input of the next in series. The main difference here is that we connect the complement output of each flipflop to the clock input of the next. However, we still monitor the normal flipflop outputs to determine the count stored there. With this arrangement, the count sequence shown in Fig.6 is obtained. The table shows the counter starting with the maximum count stored in the flip flops (1111 ). When the count is decremented to zero, the next input pulse simply flips the counter back to its maximum count value of 1111. The cycle then repeats. Down counting is illustrated in the timing waveforms of Fig.7. Those output waveforms are the ones that occur at the normal flipflop outputs. Since the complement flipflop outputs are not shown, it is more difficult to trace the operation of that counter. If you'd like to see how each input pulse causes the toggling and triggering of each flipflop in sequence, simply draw the complement signals to each of the MARCH 1988 83 A IN T COUNT CONTROL Fig.8: a 4-bit binary up/down counter. When the count control signal is high (binary 1), the circuit is an up counter. When the count control signal is low, the circuit is a down counter. waveforms in Fig.7 before doing a pulse-by-pulse analysis. Keep in mind that a down counter can also include preset circuitry so that it may begin decrementing from some particular value. By adding some logic circuitry to the counter you can make it count up or down. This is illustrated in Fig.8. An up/down COUNT CONTROL line is added to determine the direction of counting. If a binary 1 is applied to that input, the counter will count up. This binary 1 enables all of the A gates and it causes the normal flipflop outputs to pass through the gates to the clock (T) inputs of the next flipflop in sequence. If the up/down control line is made binary 0, the B gates are enabled by the inverter and the A gates are inhibited. This causes the complement outputs to be passed through to the clock inputs. The counter then counts down. While binary counters can easily be made up of in' 192, ' L192,'LS192 ( 13) BO RR OW ! 12J CAR RY O UTPUT OUTPUT dividual flipflops and gates, that is rarely done anymore. The integrated-circuit manufacturers have already constructed binary counters in a variety of configurations, usually in multiples of four or eight bits. TTL, CMOS and ECL ICs are available, including those with presetting, down counting, etc. A Typical IC Counter One of the most-used IC counters is the 4-bit MSI device shown in Fig.9. The device is a 4-bit binary up/down counter with presetting. In other words, it incorporates all the features we discussed previously. The counter has four outputs and four parallel data lines are used for applying a preset input. The loadinput line causes the parallel binary word applied to the data inputs to be loaded into the flipflops. The counter also has a clear line for resetting it to zero. Instead of having a single count input like the up/down counter discussed previously, this device has two inputs. To decrement the counter, you apply input pulses to the down-count input. To increment the counter, you apply pulses to the up-count input. Carry and Borrow c~~~~ .o:<•:c._ 1 - - - I > <>-+ttt-1-t-t---+t---, UP !SJ COUNT DA TA 19) INPUT D The carry and borrow outputs have not been discussed previously. These are used when counters are cascaded. The carry output is produced by an AND gate that looks at the normal flipflop outputs. It detects when the counter content is 1111 which is the maximum value. The next input pulse will cause it to return to zero. When this happens, the carry output generates a pulse which is applied to the next counter in series, so that the overflow will be recorded. The borrow output is used for cascading counters in a down count application. The borrow output signal is generated by an AND gate that monitors the complement outputs of the flipflops. When the counter is decremented to 0000, the borrow output signal is generated and applied to the down count input of the next counter in series. With those signals, multiple counters can be cascaded to form binary counters with lengths of 8, 12, 16, 20 or any other multiples of 4 bits. BCD Counters Fig.9: schematic diagram for the Texas Instruments 74192 4-bit binary up/down counter. 84 SILICON CHIP While such counters are useful, there are many situations where it is desirable to use a decimal-like representation. To cope with this problem, some special binary codes have been developed. The most popular of those is binary coded decimal (BCD). BCD is BCD DECIMAL D C 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 0 0 0 0 1 1 B A 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 0 0 0 0 1 Fig.10: decimal to binary-codeddecimal (BCD) equivalents. 0 still a binary code in that decimal values are represented with binary numbers but only the decimal numbers 0 to 9 are used. The BCD code is shown in Fig.10. Decimal numbers are represented by 4-bit BCD numbers, one for each digit. For example, the number 729 in BCD is 0111 0010 1001. By using flipflops and gates it is possible to construct a BCD counter - that is, one that counts by tens. It has 10 states, 0 to 9. Such a counter is called a BCD counter, decimal or decade counter; you see one in Fig.11. Notice that the first three flipflops are cascaded in a standard 4-bit binary counter with the normal output connected to the clock input of the next flipflop in the chain. The last flipflop, on the other hand, has its clock (T) input connected to the normal output of the A flipflop. Note that the signal controlling the J input on the D flipflop is dervived from an AND gate that monitors flipflops Band C. Note also that the complement output of the D flipflop is fed back to the J input of the B flipflop. The result of all these unusual interconnections is that the counter has only ten states instead of the usual 16 for a 4-bit counter. The counter counts in the BCD sequence previously described in Fig.10. The waveforms generated by the BCD counter are shown in Fig.12. The counter counts from 0 (0000) to 9 (1001) in the normal sequence. When the tenth input pulse is received [trailing edge), the counter returns to 0 and the sequence repeats. While it's possible to construct a BCD counter from individual gates and flipflops, there's no need to bother since such devices are available as single integrated circuits. Most of these feature a master clear or reset line and many feature both presetting and up/down counting capabilities. To count values higher than 9, BCD counters may be cascaded as shown in Fig.13. The first BCD counter then counts in units of Oto 9. After 10 input pulses occur, the MSB output of the first counter (ie, the D output) triggers the next counter in sequence. The second IN .I. 1 A o o oI ............... _ co OO 0 0 1 1 1 ...~o~o_l_o 0 0 0 0~ I Fig.12: input and output waveforms for a BCD counter. counter represents the tens decade and is incremented every 10 input pulses. The tens counter in turn drives the hundreds counter. Additional counters can be added for thousands, tens of thousands, hundreds of thousands and so on. To read the content of the counter, you observe the BCD codes at the counter outputs. For example, the number stored in the counter shown is 853. Note that in reading the output of a BCD counter, the 4-bit groups are separated from each other. The output is three 4-bit BCD numbers (1000 0101 0011). Just as you can use binary counters for frequency division so can you use BCD counters for that application. The circuit shown in Fig.13 will produce frequency division by some multiple of 10. The first BCD counter will divide the input frequency by 10 (ie, its D output will be one-tenth the frequency of the input). The second counter will produce division by 100 while the third will produce division by 1000. Both binary and BCD counters can be used in counting and frequency dividing applications at very high frequencies. Standard TTL MSI counters can achieve speeds upward of 50MHz while Schottky TTL counters can achieve speeds up to 125MHz. CMOS counters have a much lower limit of approximately 25MHz, but progress is being made in extending this. ECL counters are available for frequencies up to 2GHz. Shi£t Registers Another sequential circuit made up of flipflops is the shift register. Like a counter, multiple flipflops are used to store a binary word. However, the flipflops are interconnected in such a way that incrementing and LEAST 1100 SIGNIFCANT A B C D DIGIT (LSD) COUNT IN Fig.11: schematic diagram for a BCD counter. All unused J and K inputs are connected to binary 1 (high). 0 II 1 1 0 1 0 A B C D BCD COUNTER BCD COUNTER UNITS TENS MOST SIGNIFICANT DIGIT (MSD) HUNDREDS Fig.13: cascaded BCD counters MARCH 1988 85 IN SHIFT (CLOCK) Fig.14: logic diagram for a 4-bit shift register. decrementing counting operations are not achieved. Instead, the connections are such that the binary word stored in the counter is shifted either to the right or to the left. In other words, as each clock pulse occurs, the bit stored in one flipflop is shifted into the flipflop next to it. A common 4-bit shift register is illustrated in Fig.14. All the clock (T) inputs are connected together to a single line. The normal and complement outputs of one flipflop are connected to the J and K inputs respectively of the next flipflop in sequence. A single input line is used for entering data into the shift register a bit at a time. Shift registers are used to deal with serial data words. A serial pulse train, that occurs in synchronism with the shift clock pulses, applied to the input will be entered into the shift register a bit at a time. This is illustrated in simplified form in Fig.15. The individual blocks represent each of the flipflops in the shift register. All the flipflops are initially reset. When the first clock pulse occurs, the first bit in the serial pulse train at the input will be shifted into the first flipflop. A binary O is shifted out of the D flipflop. As each shift clock pulse occurs, the next bit is shifted into the register. The first bit moves over to flipflop B to accommodate the new input bit. After four clock pulses have occurred, the entire serial word is then contained in the shift register, as shown. Holding the input line at zero and applying four additional shift pulses will cause the binary number stored in the shift register to be shifted out a bit at a time, thereby generating a serial output word. The process is illustrated in Fig.16. As you can see, the shift register can be used to accept, store and generate serial binary data words. One of the most common applications for a shift 1101 register is serial-to-parallel data conversion. A serial data word can be shifted into the shift register. If the outputs of the individual flipflops are available, then that word will appear as a parallel data word as shown in Fig.17 A. If the flipflops in the shift register have presetting circuitry similar to that described earlier for binary counters, then the register can be loaded with a parallel binary number. Once the shift register is preset with the parallel number, shift pulses will shift the word out a bit at a time. This creates a serial version of the parallel input word. Thus, the shift register accomplishes parallel-to-serial data conversion as shown in Fig .17B. Like counters, shift registers are available as prepackaged circuits in a variety of forms. MSI devices with four and eight bits are common. Those feature preset, clear, shift right, or shift right and left. Larger shift registers can be created by simply cascading 4 - and 8-bit devices. For example, a 32-bit shift register can be created by cascading four 8-bit devices. Very large LSI shift registers are also available for special applications. For example, a 256-bit MOS shift register is available for memory applications. Such a register is not used to store a single 256-bit word. Instead, it is used to store many smaller words. For example, a 256-bit shift register can store 256 -;- 8 = 32 bytes. Those bytes are retained in the shift register flipflops end to end as illustrated in Fig.18. The data is entered serially and read out serially. Because there are so many flipflops, parallel output is not feasible. Fig.19 shows a circuit for using the 256-bit shift register as a memory. The gates at the input of the shift register are used for entering serial data when it is desired to store a byte and for data recirculation. When clock pulses are applied to a shift register, data that is shifted out is generally lost. However, it doesn't have to be. By taking the serial output of the shift register and feeding it back into the shift register input, the serial word will be restored at the input as it is read out. This is accomplished with gates A and Cat the input to the shift register. The CONTROL line is used to select whether new serial data is to be stored or whether recirculation is to be accomplished. When the CONTROL input is high, the shift register lolololol ORIGINAL STATE Fig.15: how serial data is entered into a shift register. o-1 oI oI111 1o, 11lol1lololoo 2ND 2ND o-1 oI oI o1, 1, o, 1l1lol1lolooo 3RD 3RD 1,1,101110000 4TH 86 . SILICON CHIP Fig.16: how serial data is removed from a shift register. o-!o I olo lo 11011 4TH 1 A 0 1 0 RECIRCULATE mJ 101ololojojoj ORIGINAL STATE AFTER 4 SHIFT PULSES 256•BIT SHIFT REGISTER Bffl ORIGINAL STATE 0 1 1 SERIAL OUT ~ AFTER PRESET Wr90~0110 0 0 1 1 0 CLOCK Fig.17: shift register applications for (A) serial-toparallel conversion and (B) parallel-to-serial conversion. IN ---i BYTE BYTE BYTE 31 30 29 I 1 BYTE ADDRESS o=D---ouT BYTE BYTE BYTE 2 1 0 Fig.18: a 256-bit shift register used as a serial memory to store 32 bits of data. will recirculate. Serial data output is fed to gate A which is enabled by the control line. This passes through OR gate C to the shift register input. During this time, any new serial data is ignored by gate B which is inhibited by the inverter operated by the CONTROL line. To enter new data, the CONTROL line is set to binary 0. This enables gate B and inhibits gate A. No recirculation will take place. However, as the shift pulses are applied, the new serial byte to be stored will be shifted in a bit at a time. To keep track of where the different bytes are stored in the shift register memory, the circuit in Fig.19: a 256 bit shift register used as a memory bank. Fig.19 uses a 3-bit binary counter and a 5-bit binary counter. The 5-bit binary counter is a word counter and its output is a 5-bit binary word we call the address. Remember we said that it is possible to store 32 bytes in a 256-bit shift register. We label those bytes byte O to byte 31. The 5-bit counter has a maximum count capability of 31, therefore, the address appearing at the output of the counter designates which byte appears to the far right of the shift register, ready to be shifted out. The 3-bit binary counter is used to count clock pulses. This 8-state counter counts to eight for each byte stored or read out. Reproduced from Hands-On Electronics by arrangement. Gernsback Publications, USA. ~ © SHORT QUIZ ON DIGITAL FUNDAMENTALS 1 . A 4-bit binary up counter is preset to 001 0. Seven input pulses occur. The decimal value of the counter content is: c. 9 a. 2 d. 11 b. 7 2 . The maximum number of states that a 6-bit counter can represent is _ _ _ _ _ __ _ __ 3. The maximum number count capability of a 7-bit counter is ___________ _ _ __ 4. A 3-bit binary counter is cascaded with a BCD counter. An input frequency of 400kHz is applied to the circuit. The output frequency is _ _ _ kHz. 5. How many BCD counters does it take to represent the number 1 9, 900? a. 2 c. 4 b. 3 d. 5 6. A 4-bit binary down counter is preset to 0011 . Six input pulses occur. The binary value of the counter content is: a. 0011 c. 1010 b. 0110 d. 1101 7. Clearing a counter or shift register means the same as presetting it to _____ _ _ _ __ LESSON 5 8 . The maximum count of a 4-bit BCD counter is: a. 1000 c. 101 O b. 1001 d. 1111 9. Counters and shift registers are a type of _ _ logic circuit. 10. List four ways that data can be entered, stored and read out of a shift register . a. c. b. d. ANSWERS ino repas 'U! 1a1reJed ·p ino 1a11eJed 'U! 1epas ·o lno 1a11eJed 'U! 1a11eJed ·q ino 1epas 'u! 1epas ·e ·o L 1e11uanbas ·6 (6 1ewpap) LOO L ·q ·g OJaZ 'L .( LO L L '0 L L L ' L L L L '0000 ' LOOO 'O LOO Oj S8W!l X!S pa1uawaJoap S! L LOO) . LOLL ·p ·(1!6!P lpea JOJ Ja\unoo 0:)8 auo) g ·p 'ZH)j9 = 08 ~ ZH)jQQv ·o L Aq Ja\unoo 088 a41 pue g /4q sap!A!P Ja\unoo 11q•£ a41 'ZH)f9 LG L = L - (G X G X G X G X G X G X G) = L - LG v9 = G x G x G x G x G x G = gG 6 = L + G = L + 0 LOO JO '. 6 ·o MARCH 1988 ·g ·g ·v '8 ·G .L 87