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.. ~ --·r , T ~==..D. !'---~,.,.........._........... ~., . ,-I G . . -1.·.·.T· · . A. .I.J T [-'· 1 1 ~ ·t :Jl '1: [>~--.-:_,,...... _, T:1 ·M ·: ·N. rr_• -~"}L .. . . J. ;I1. _ _ 0; '. · A· ·-s - -".-,_._ E --- - 1 ~T··· ----h --·= ~h-. By Louis E. Frenzel The basic circuit for storing binary data in digital circuits is the flipflop. In a previous lesson, you saw how flipflops could be combined to form storage registers capable of remembering a binary word of any length. You also saw how flipflops could be combined to form counters and shift registers where binary numbers could be manipulated in a variety of ways. All digital equipment contains one or more counters or registers to store and manipulate binary data. But as you probably know, there are some kinds of digital equipment that require the ability to store large amounts of binary data. The most obvious example, of course, is the digital computer which has memory capable of storing many thousands of instruction and data words. Other kinds of digital equipment also have the need to store large amounts of data. To meet that requirement, special electronic memory circuits have been developed. Like counters and registers, some of those memory circuits are made up of flipflops. In other memory circuits, different kinds of storage elements are used. In this lesson, you'll learn about integrated circuits designed specifically for storing large amounts of digital data, and how they are used in computers and other digital equipment. Memory Organisation and Operation An electronic memory is a place where hundreds or thousands of binary words may be stored. The memory is divided up into discrete locations where a fixed-size binary number may be stored. Those individual word-storage locations are , in turn, made up of bit memory elements such as flipflops and other cir84 SILICON CHIP cuits [which we'll discuss later). The organisation of such a memory is illustrated in Fig.1. Its two key characteristics are the number of bits per word and the total number of word-storage locations. Most electronic memories are capable of storing standard binary word sizes such as 4, 8, 16 and 32-bits long. Of course, other sizes can be created. The total word-storage capacity of a memory also varies widely. Typical sizes are 256, 1024, 4096, 16,384 and 65,536 words. You've probably recognised that all those memory sizes are some power of two. But the word length and memory size are dependent upon the application in which they are used. To describe memories, we use a shorthand notation that gives both memory and word sizes. For example, the designation 1024 x 4 refers to a memory containing 1024 4-bit words; the designation lK x 4 is used to define the same memory. In other areas of electronics, k usually means 1000, but in memory jargon, K = 1024 - which is an even power of two. STORED DATA 1 0 1 0 1 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 0 1 MEMORY LOCATION 4093 .....----------------. 4094 1 1 1 0 0 0 1 1 4095 1 1 1 1 1 1 1 1 Fig.1: this illustration of the organisation of a memory chip - which is capable of storing 4K or 4096 bytes of data - shows that the chip is made up of lots of storage locations, each having a distinct address (0-4095). NUMBER OF BITS IN ADDRESS WORD NUMBER OF MEMORY LOCATIONS 8 256 10 1,024(1K) 12 4,096(4K) 16 65,536(64K) 20 1,048,576(1M) 24 16,777,216(16M) 32 = = 4,294,976,296(46) = = K KILO WORDS 1,024 M MEGA WORDS 1,048,576 G = GIGA WORDS = 1,073,741,824 Fig.2: unlike other areas of electronics where lk represents 1000, 1K in memory jargon means 1024. Using that method, any memory size can be designated. For example, a memory capable of storing 65,536 bytes would be designated as 64K x 8; a 256K memory for 32-bit words would be designated 256K x 32. Address To locate a specific word in memory, each word is given a unique number called an address. In Fig, 1, for example, the 4K x 8 memory has 4096 storage locations, numbered from Oto 4095, for byte-length words. The numbers are the addresses, and are used for each specific storage location. To use an electronic memory, you first apply an address to it. The address is a multi-bit binary word. A specific number of address bits are required to address the memory locations. For example, with a 12-bit address, 4096 individual states can be defined (2 to the 12th power = 4096), which means that a 12-bit word would be used for the address of the 4K memory in Fig, 1. A 16-bit address would permit up to 64K (65,536) memory locations to be addressed. The table in Fig.2 shows the number of locations different word sizes can address. Random-Access Memories The memories that we've just discussed are generally referred to as random-access memories (RAMs ). As this name implies, any specific memory location may be accessed at random. Early computer designs used a serial data-storage format , which required that data stored in memory be accessed sequentially. A given word could not be directly selected; instead it was necessary to wait for that word to come around. Today's electronic memories are parallel devices and any given memory location may be accessed directly without reference to any other memory location. Random-access memories break down into two basic types: read/write and read-only memories . The read/write device permits both storage and retrieval operations to take place. New data may be stored in any memory location and any location may be accessed and recalled. Such memories are generally ref erred to as random-access memories or RAM for short. The other type of random-access memory is the read-only memory or ROM. Data is permanently stored in such memories. The desired data is stored in memory at the time that the circuits are manufactured but in some ROMs, the data may be stored later by the user. Once that data is written into the memory, it cannot be destroyed or changed; because of that, only read operations are possible thereafter. There are many applications where it is desirable to permanently store data or programs. Read-only memories are said to be non-volatile because their contents are retained even when power Store and Recall Operations Once the address has been applied and a specific storage location enabled, a read or write operation is performed. A read operation simply means that the binary number stored in the addressed location is recalled - ie, read out or transferred for use elsewhere. The read operation is non-destructive, in that the contents of the addressed memory location are retained. A write operation is the process of storing new data in the addressed memory location; the operation is equivalent to loading a storage register. Access Time The most important specification of any memory device is its access time - the time it takes for a word stored in a memory to be addressed and read out. It is that interval between the application of the address and the appearance of the data at the output. Most MOS memories have access times in the 100-500 nanosecond (ns) range. Bipolar TTL memories have access times in the 20 to 90ns range. ROW SELECT COLUMN SELECT 7 07 WAITE AMPLIFIER 1 3,STATE CONTROL WAITE AMPLIFIER 2 Fig.3: this diagram of a single storage element in a static memory chip illustrates the operation of each cell in the memory. In the static-memory cell, the storage element is a flipflop. MAY 1988 85 is removed from the circuit. In read/write memories all data stored in the memory is lost when power i~ turned off; such memories are said to be volatile. Despite the fact that both read/write and read-only memories are of random-access organisation, read/write memories are usually referred to as RAM and read-only memories are simply called ROM. Both types will be discussed in detail in the following sections. RAM Storage Cells ADDRESSED COLUMN t COLUMNS ROW s I I ACTIVATED MEMORY CELL Fig.4: most semiconductor memories are organised as a matrix of storage cells. To access a particular cell, one row and one column must be activated. SILICON CHIP WRITE AMPLIAER STORAGE CAPACITOR There are two basic types of storage cells or elements used in read/write memories - static and dynamic cells - both of which store one bit. Each type has its advantages and disadvantages. In most cases, the memory cells are made up of metal-oxide semiconductor field-effect transistors (MOSFETs ). Each storage element is capable of storing one bit. Many thousands of storage cells can be fabricated on a single silicon chip. By combining a number of the chips, you can form a memory of any desired size. Let's take a look at how the static and dynamic cells work. Fig.3 shows a diagram of a typical static memory storage cell. The basic storage circuit is a latch or flipflop made up of enhancement-mode MOSFETs Ql-Q4. Ql and Q2 are the active transistors, while Q3 and Q4 have been biased into conduction and act strictly as load resistors. The circuit in Fig.3 has two stable states. One state is where Ql is conducting and Q2 is cut off. With Q2 cut off, the supply voltage through Q4 on the gate of Ql keeps Ql conducting. With Ql conducting, its drain is near O volts and below the conduction threshold of Q2. Therefore, Q2 remains off. The other stable state is where Q2 is conducting and Ql is cut off. With those two states, either a binary 0 or binary 1 can be represented. The gate to source capacitances of Ql and Q2 are charged through either Q3 or Q4 to keep the conducting transistor on. All the additional circuitry in Fig.3 is used for storing data in the cell or reading it out. Transistors Q5 and Q6, as well as Q7 and Q8, are switches used for addressing purposes. 86 DATA OUT I DATA IN Fig.5: the architecture of a dynamic storage cell differs somewhat from that of a static unit. Here, miniature capacitors, which must be refreshed periodically, are used as the storage elements. In most memories, each storage cell is part of a matrix of storage cells arranged in a row and column format. To address a particular cell, address signals activate the desired row and column in which the cell appears (see Fig.4). In Fig.3, when a binary 1 is applied to the row-select line, transistors Q5 and Q6 conduct, allowing the signals at the drains of the flipflops, X and X-bar, to be passed through to Q7 and Q8. When the column-select line is binary 1, Q7 and Q8 are also turned on. At this point, the latch output signals pass through Q5 and Q7 as well as Q6 and Q8 and appear at the inputs to the sense amplifier. The binary state stored in the flipflop appears at the sense amplifier output. Usually, the sense amplifier is a 3-state device whose output can be turned off or effectively disconnected from the output so that the memory cell can be used in bus configurations. To write data into the circuit, both the row and column-select lines are made binary 1 so that transistors Q5-Q8 conduct. The data to be stored in the circuit is then applied to the data-input line. For example, to store a binary 0, a binary O is applied to the datainput line. The signal is then applied to write amplifier 1, and to write amplifier 2 through an inverter. That results in write amplifier 1 delivering a zero, while amplifier 2 delivers a 1. The zero output of write amplifier 1 pulls the drain of Ql low. Since Q5 and Q7 are conducting, they appear to be a near short circuit and therefore regardless of the state of the latch, the drain of Qi goes to binary 0. That turns Q2 off if it should happen to be on, which in turn, causes Ql to conduct. The circuit then holds that state, storing a binary 0. If a binary 1 were applied to the data input, the output of write amplifier 2 would be binary 0 , causing the drain of Q2 to be pulled low through Q6 and QB. The drain of Ql (X) would go high and so the circuit would store a binary 1. The basic storage element in a dynamic memory cell is a capacitor. When the capacitor is discharged, it stores a binary 0. When the capacitor is charged, it stores a binary 1. Dynamic memory ICs pack thousands of tiny capacitors on the chip with related control circuits to read and write information. RAS TIMING AND CONTROL CIRCUITS ----------- ..... I I I ADDRESS STORAGE REGISTERS INPUT ADDRESS A0-A7 ROW CIRCUITS I I ROW DECODERS 256x256 STORAGE MATRIX SENSE, WRITE/ REFRESH AMPLIFIERS BUFFER FF DATA OUT COLUMN DECODERS COLUMN DATA IN (D) FF Fig.6: functional block diagram of a 4164 64K x 1 dynamic RAM IC. Such a circuit is said to be volatile because without refreshing (ie, period recharging of the storage capacitors), all data stored in memory would be lost. Note that the IC contains on-chip refresh circuitry. A simplified drawing of a typical dynamic storage cell is shown in Fig.5. Transistors Ql and Q2 are switches that permit access to the storage capacitor. As in most memory architectures, dynamic cells are arranged in the form of a matrix with rows and columns. To access a given memory cell, the specific row and column in which it appears is activated by row and column-address signals. In Fig.5, the row-address signal is applied to Q2 and the column-address signal is applied to Ql. When the transistors are turned on by the address signals, data may be stored in or read out of the capacitor. If data is to be stored, it is applied to the data-input line and passed through the write amplifier, which causes the capacitor to charge or discharge through Ql and Q2. To read data out, the charge stored on the capacitor is simply connected to the read-amplifier input through Ql and Q2. The capacitance of the tiny capacitor in each storage cell is only a fraction of a picofarad. But while it is very small, it's still capable of holding a charge that can determine the binary state of the cell. However, leakage in the circuit causes the capacitor to discharge over time, despite the fact that MOSFET circuits are typically very high impedance in nature. The effect of such leakage is that the state of the cell changes over time. Of course, such a memory is not reliable. To overcome the problem, dynamic memory cells are periodically refreshed. That is, special circuitry in the dynamic memory periodically looks at the state of the cell and refreshes it - either charging or discharging the capacitor as required. In most memory ICs, the refresh operation takes place approximately every two to four milliseconds. The refresh circuitry reads the state of the cell and reapplies it to ensure data integrity. The entire refresh operation is transparant to the user who never knows that it's going on. Typical RAM ICs Now let's take a look at some typical static and dynamic memory ICs. Many manufacturers supply a wide variety of memory-chip configurations. However. over the years some configurations have become more or less standard. For example, most dynamic RAMs come in one of four configurations: 4K x 1, 16K x 1, 64K x 1 and 256K x 1. The 64K x 1 chip contains 65,536 storage locations for 1-bit binary words. Naturally, to form large memories, many chips must be placed in parallel. To form a 64K x 8 memory would require eight such chips. Static-memory circuits are available in a wider range of configurations. But because static-memory cells contain many more components, they take up much more space on a chip. As a result, static memories typically are capable of storing less data than dynamic RAMs. Today, a practical commercial dynamic RAM is capable of storing up to 256K bits. Typical static RAMs have a maximum storage capacity of 64K bits. As for memory organisations, static RAMs are available in some of the following configurations: 4K x 1, lK x 4, 4K x 4, 4K x 16 and 8K x 8. An example of a dynamic memory is Texas Instruments' popular 64K x 1 dynamic RAM, the 4164. That chip, made by many manufacturers under different model numbers, is widely used for personal computer memories. Housed in a standard 16-pin dual-in-line package (DIP), it operates from a single + 5V supply, and has a typical access time of 150ns. A simplified block diagram of the 4164 is shown in Fig.6. The dynamic memory cells themselves are organised into a matrix of 256 rows and 256 columns capable of storing 65,536 bits. Note that the 4164 has 8 lines labelled AO to A7. With eight a ddress bits, 256 separate locations can be addressed. The question is: how do we address the full 64K? To address 64K bits requires a 16-bit address. The 16-bit address is fed to the chip as two 8-bit segments. The eight least significant bits of the address are first applied to the address line and are strobed into the row address register with a control signal called RAS (row address strobe). The higher order eight bits of the address are then placed on the eight address lines, loaded into memory by the control signal, CAS-bar (column address strobe), and stored in the column-address register. Both the row and column-address registers feed row and column decoders that convert the eight address bits into 256 lines. One column-decode and one rowM A Y 1988 87 WE A3 A4 AS A6 ROW DECODER 64x6~fitll~AGE (4096 CELLS) uo CIRCUITS DATA INPUT/OUTPUTS A7 AS COLUMN DECODER AO A1 A2 A9 Fig.7: block diagram of the 2114 4K-bit RAM, which uses a 10-bit address code; six address lines (A3 to A8) for the row decoder and four address lines (AO, Al, A2 and A9) for the column decoder. decode output is required to activate each memory cell. Once a particular memory cell has been addressed, a read or write operation is then performed. The W-bar input line selects the mode. If W-bar is high, a read operation is performed; if it's low, a write operation is performed. Assuming that a read operation has been selected, the addressed storage cell will be enabled. A sense amplifier reads the charge stored on the cell capacitors and passes it through to a data-output flipflop. For a write operation, W-bar is made binary 0. The bit to be stored in the selected cell is placed on the D-input line and stored in a flipflop. When control signal CAS-bar goes low, the data is stored in the selected cell. Finally, keep in mind that, because this is a dynamic memory circuit, a refresh operation must be performed. In the 4164, a refresh operation is performed approximately every four milliseconds. The row address is incremented by an external counter and after each count, the RAS line is strobed, which causes the 256 bits in each row to be refreshed. Static RAM The 2114, a popular 4K-bit static RAM, is organised in a lK x 4 configuration; ie, it can store 1024 4-bit words. Since the 2114 can address 1024 words, it uses a 10-bit address word. Housed in an 18-pin DIP, it operates from a + 5V supply, and has a nominal 250ns access time. Fig. 7 shows a simplified block diagram of the 2114. The memory cells are arranged in a 64 x 64 matrix. producing 4096 individual storage cells. Six of the address bits A3-A8 are applied to a row-select decoder that's used to enable the 64 rows of storage cells. The other four address bits (AO, Al, A2 and A9) are applied to a column decoder. The 16-column decode outputs are used to enable 16 4-bit words, as illustrated in Fig.8. For a given address, one of the 64 rows will be enabled. The column decoder enables four columns simultaneously, thereby defining a 4-bit word in the selected row. In this memory, four pins are used for both input and output (I/0). The write-enable (WE) input signal 88 SILICON CHIP determines whether a read or write operation is to be performed. If the WE signal is low, a write operation is performed. The data on the four I/O pins are accepted as inputs and stored in the memory locations selected by the address. When the WE line is high, a read operation is designated. The 4-bit word stored in the location designated by the address is read out and placed on four I/O pins. A chip-select (CS) signal is used to enable the chip. When CS is high, the chip is disabled and no read or write operations take place. However, when CS is low, the chip is selected or enabled and a read or write operation may occur. Read-Only Memories A read-only memory (ROM) is a semiconductor circuit in which a number of binary words has been permanently stored. An input address selects the desired word to be read out. Read-only memories are used in those applications where it is desirable to permanently store binary information. In a computer, for example, it is usually desirable to incorporate a ROM that contains instructions that make up frequently used programs. In that way it is not necessary to load those programs into the computer's RAM from some external peripheral device. ROMs are also used in various logic applications. By assuming that the address lines are inputs and the data lines are outputs, the ROM can be considered as a form of combinational logic circuit. By storing specific bits in the ROM, it can perform a wide variety of special functions, such as code conversion and table-look-up functions, which are less conveniently implemented with more conventional combinational logic circuits. Diode Matrix ROM To better illustrate the concept of a ROM, refer to the circuit in Fig.9, a simple 8 x 4 ROM. It stores eight 4-bit words. A 1-of-8 decoder circuit is used to translate a 3-bit address word into eight output lines. In this particular circuit, for a given address, only one output line will be active. The decoder has active-low outputs, which means that the enabled output line will be binary O while all other output lines are binary 1. The data is stored in ROM by the presence or absence of a diode. Whenever a binary O is desired in one of the words, a diode is connected between the decoder output and the ROM output line where the O is desired. Assume that the input address is 001. That COLUMNS ADDRESSED 4-BIT WORD LOCATION "'-1T } ROWS~ 64x64- MATRIX Fig.8: the 2114, with its 1K x 4 configuration, can store 1024 4-bit words. The memory is arranged in a 64 x 64 matrix, providing 4096 individual storage cells. 1 OF 8 DECODER \ ACTIVE LOW OUTPUT D(MS8) C B A(LSB) Fig.9: in this illustration of a ROM, the presence or absence of a diode determines whether a 1 or a O will be sensed when a particular memory location is accessed. means that the 1 output line will go low, causing diodes Dl, DZ and D3 to conduct. Therefore, they effectively bring the output lines to which they are connected low. Since all of the other decoder-output lines are high, the remaining diodes in the network are cut off. Therefore, the other output lines are high at this time. The output word DCBA is thus 0100. While small simple ROMs can be constructed using the diode-matrix technique, prepackaged ROMs are used in most applications because they're capable of storing many more bits of data and are far more useful. There are two basic types of ROMs: maskprogrammable and electrically-programmable. Maskprogrammable devices are programmed during the manufacturing process. A special mask, conforming to the bit pattern stored in memory, is custom-designed to interconnect the circuits on the ROM chip. In other words, the data to be stored is permanently manufactured into the device and cannot be changed. Electrically programmable ROMs. called PROMs (programmable read-only memory) can be programmed by the user. When the ROM comes from the manufacturer, it contains all binary 0's or all binary 1 's depending upon the circuitry involved. The user places the ROM in a special programming instrument called a PROM programmer and enters the data to be stored. In some cases, data storage is permanent. At other times. data storage is semi-permanent: that is. the data remains in memory even when power is removed from the circuit, but can be erased or reprogrammed. In high-volume production applications, where the information to be stored is reliable, masked ROMs are to be preferred because of their very low cost. On the other hand, where the data to be stored may have to be changed for some reason, PROMs are preferred. During the design process of any equipment using a ROM, the program or data may change several times as the "bugs" are worked out or as performance is improved. Even in production units, it may be desirable to update the ROM if an important change occurs. In such applications, PROMs are preferred. However, PROMs are far more expensive than masked ROMs for most applications. During the development process though, nothing can beat a PROM for flexibility and ease of up-dating. Both masked and programmable ROMs are made with both MOS and bipolar technology. Most ROMs are of the MOS variety because of their low cost and high storage density - currently up to 256K bits per chip. On the other hand, bipolar ROMs are much smaller. Because· the circuitry is more complex and dissipates more power, it takes up more space on the chip; thus, fewer bits can be stored. Most bipolar ROMs are small and are limited in practice to only several thousand bits. The big advantage of the bipolar ROM over the MOS ROM is speed. Access time for a typical MOS ROM is in the 200 to 500 nanosecond range, while bipolar ROMs have access times of typically less than 100 nanoseconds. In fact, bipolar ROMs with access times in the 20 to 50 nanosecond range are available for high speed applications. In most applications, you will encounter the MOS ROM, which is available in a wide variety of sizes. The main difference between ROM and RAM organisation is that while typical dynamic RAMs are designed to ADDRESS{ INPUT ROW DECODER BIT LINE 02 DATA OUT COLUMN DECODER ~ ADDRESS INPUT Fig.10: in this simplified diagram of one type of ROM structure, the presence or absence of a MOSFET transistor (Qt in this example) at each possible junction determines whether 1 or O is stored. If a MOSFET exists (ie, is connected) at the junction, a binary 1 is stored; if not, a binary O is stored. MAY 1988 89 store multiple 1-bit words, ROMs are usually organised to store bytes (eight bits). Typical ROM storage configurations are 1K x 8, 2K x 8, 4K x 8, BK x 8, 16K x 8 and 32K x 8. COLUMN Masked MOS ROM Most MOS ROMs use the row and column matrix structure discussed earlier. Two sets of decoders, one for rows and another for columns, are used to address a matrix of storage elements. The state of the storage elements determines whether a binary 1 or binary O is stored. Fig.10 shows a simplified diagram of one type of ROM structure. In this circuit, the presence or absence of a MOSFET (Ql) at each possible matrix junction determines whether a binary 1 or a binary 0 is stored. If the MOSFET exists, a binary 1 is stored. If the MOSFET does not exist, a binary O is stored. MOSFETs exist at every junction but the mask determines which ones are connected and which are not connected. In connection with the MOSFET transistor storage elements, another transistor (QZ) is associated with each column. The column decoders turn the MOSFETs on or off as required. To select a particular bit in ROM, an address is given to the row and column decoders and each, in turn, activates one line. If the output of the activated row decoder is binary 1, Ql (if it exists) is turned on, causing a binary 1 to appear on the bit line. The column decoder output turns on QZ. Therefore, the sense-amplifier output will see ground or binary O through Ql and QZ. The output, therefore, will be a binary 1. If the transistor, Ql, does not appear in the matrix, effectively an open circuit exists. The bit line being open causes an open condition to appear at the output amplifier if QZ is turned on, placing a binary O at the output. Bipolar PROMs Bipolar ROMs are made programmable by placing a fuse element in the circuit as illustrated in Fig.11. Note that the output of a decoder is used to enable a bipolar transistor at each matrix junction. The emitter of the transistor is connected to the column output line RCA Radio Pty Ltd is the only company which manufactures and sells every PCB & front panel published in SILICON CHIP, ETl & EA. 651 Forest Road, Bexley, NSW 2207 Phone (02) 587 3491 for instant prices 4-HOUR TURNAROUND SERVICE 90 SILICON CHIP ADDRESS INPUT l----+----3~-+----+-___;.,_ROW OUTPUT AMPLIFIERS v DATA OUTPUT Fig.11: bipolar ROMs are made programmable by the inclusion of a tiny nichrome or silicon fuse which is placed between the transistor emitter and the column output line. If the fuse is good and the output of the decoder is high, the transistor turns on and a binary 1 is applied to the output amplifier. through a tiny nichrome (an alloy of nickel and chrome) or silicon fuse. If the output of the decoder is high, the transistor turns on. If the fuse is good, a binary 1 is applied to the output amplifier; that results in a binary O output. To cause a binary 1 to appear at the output, the fuse can be blown. A high current is passed through the fuse which causes it to open. Now when the decoder output is high, the transistor does not conduct because its emitter circuit is open. The resistor at the input to the output amplifiers holds the input low, resulting in a binary 1 at the output. Once the fuses are blown in such a PROM, data is permanently stored there and cannot be changed. The advantage of such a ROM is that it can be programmed in the lab by the design engineer or in the field by a service technician rather than at the factory. The disadvantage is that such permanence is often undesirable. During the engineering design process it may be desirable or necessary to change the data stored in the ROM. That means that an entirely new ROM must be programmed. However, this problem has been overcome by an improved kind of ROM known as the erasable PROM. Erasable PROMs Erasable programmable read-only memories (EPROMs) are a special type of MOS ROM whose data can be obliterated when necessary. The most common erasing technique is ultraviolet light. The chip is usually contained within a standard dual-in-line package. However, there's a transparent quartz window directly over the chip that physically seals and protects the chip, while allowing light to pass through. If ultraviolet light is applied to the chip for a short period of time, all the data will be erased. Typically, all the bits in the storage matrix are set to binary 1 by this process. By being able to erase the chip, it can be reprogrammed and reused. The stucture of an EPROM is similar to other MOS ROMs in that it consists of rows and columns of MOS transistors. In the EPROM, a special floating-gate MOSFET is used at each matrix junction. The floating gate means that the gate element of the MOSFET is not physically connected to anything. It is the charge on the gate that determines whether or not the MOSFET conducts or is cut off. The state of the MOSFET programs a binary 0 or binary 1 into the matrix. To program the chip, a high source-to-drain voltage is applied to each MOSFET for a given period of time, which causes an avalanche breakdown in the PN junction between the gate and the source. Current flows and some of the electrons pass through to the gate, thus giving it a negative charge. With the gate sufficiently charged, the programming voltage is removed. Now, when power is applied to the PROM, the MOSFET (P-channel) conducts. Because the gate is isolated and insulated from the rest of the structure, it retains its charge for a considerable period of time. Where the MOSFETs are conducting, binary 1 's are stored. To program binary 0's, the MOSFETs at the desired location are not subjected to the high programming voltage. To erase the stored data, the MOSFET is exposed to ultraviolet light, which removes charge on the gate. It takes approximately twenty minutes of intense ultraviolet light to completely erase the chip. Since ultraviolet light is contained within normal ambient lighting, it too can be used to erase the chip. But because the ultraviolet content of most normal lighting is low, erasure would take a considerable amount of time. Nevertheless, it does happen. Therefore, once an EPROM is programmed, the quartz window must be covered to prevent accidental erasure. A variation of the floating-gate MOS ROM is an electrically erasable version known as an EEPROM, which is programmed in the same way as the light EPROMs. The floating gate MOSFETs are charged or discharged as desired to store the desired bit pattern. To erase the EEPROM, however, an electrical pulse can be applied. The pulse, usually about 20 volts, removes the charges stored on the MOS gates. The entire chip or only individually adressed words may be erased. EEPROMs have become extremely popular because they have the advantages of permanent data storage combined with the ability to erase and reprogram by an electronic process. §;l Reproduced from Hands-On Electronics by arrangement. (c) Gernsback Publications, USA. SHORT QUIZ ON DIGITAL FUNDAMENTALS - LESSON 7 1 . An 8K x 4 memory contains how many bits? a. 8192 b. 32,000 c . 32,768 d. 65 ,536 1 0. The two basic types of RO Ms are _ _ _ __ and _ _ _ _ _ _ _ _ _ _ _ __ _ __ __ 2. The common name for a read/write memory is 11 . What binary numbers are stored in adresses 2, 3 , 5 and 7 in Fig.9? 2 _ _ _ _ _ _ __ __ _ __ _ _ _ _ __ 3 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ 5 _ _ _ _ _ _ _ _ _ _ __ _ __ _ _ __ 3 . The interval between address application and data output is called the _ _ _ _ _ _ _ __ _ ? _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ 4 . Most memory cells are organised as a _ _ __ of _ _ _ __ _ _ _ and _ _ _ __ __ _ 6. The basic storage element in a dynamic cell is a _ ______________ __ __ 1 2. Which of the following are volatile or nonvolatile? RAM _ _ _ _ _ _ _ _ _ _ _ _ _ __ ROM _ _ _ _ _ __ __ _ __ _ __ _ 7. The numerical location of a word in memory is called the _ _ _ _ _ _ _ _ _ _ _ _ _ __ _ 13. Data is stored in a PROM using a device called a _ _ _ _ _ _ __ _ _ _ _ _ _ __ 5. A static memory storage cell is a _ __ __ 8. In order to prevent data loss in a dynamic memory, a ____ operation must be periodically performed. 9 . How many words may be addressed with 8 bits? a. 256 b. 512 c. 1024 d. 2048 ANSWERS ~O ~ 14. EPROMs can be erased with _ _ _ _ __ oran _ _ _ __ _ _____ _ _ _ _ _ __ 15 . A store operation is called a __ , and a recall operation is called a _ __ __ _ _ _ _ __ _ ~ - L ~~. ~~-9 pBaJ '8l!JM ·g ~ as1nd 1-eoppa1a '!45!1 ia10JA-BJlln ·v ~ 1aww-e1601d INOHd ·s ~ 81!lBIOA-UOU -'-- !NOH am-e,oA - IN'v8 . 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