Fullscreen HTML5Med Res (??MB)HTML4

Digital Sine/Square Wave Generator; Pt.1 This new Digital Sine/Square Wave Generator uses high speed CMOS ICs and a digital filter IC to produce sine and square waves over the frequency range from 0.1Hz to 500kHz. It also features a 4-digit frequency readout and an output level control. By JOHN CLARKE In the past, if you wanted a high quality sine and square wave generator, you would have chosen a Wien Bridge oscillator design such as the one featured in the January & February 1990 issues of SILICON CHIP. This has very low harmonic distortion, a rated output of up to 10 volts RMS, and a frequency coverage from lOHz to lOOkHz. For many applications though, a much wider frequency range and a rock solid amplitude is desirable. To get these qualities, you would 16 SILICON CHIP previously have chosen a function generator. These can certainly give a wide frequency range but often have the drawback of a relatively high harmonic distortion on sine waves. Now there is a third choice, with this new Digital Sine/Square Wave Generator. You can think of it "as the function generator to use when you want something better than a function generator". Like most audio function generators, it covers a very wide frequency range - from O. lHz to 500kHz - and it does so with rock solid amplitude stability. There is no bouncing about of the amplitude as you change frequency (as is inevitable with thermistor stabilised Wien Bridge designs). Why would you want such a wide frequency range? Well, there are any number of reasons. If you are doing logic design, a clock frequency down to O. lHz (ie, one pulse every 10 seconds) can be very handy, since it lets you see the circuit work as each clock pulse arrives. And if you are working on audio or analog circuitry, the wider frequency range of this generator can be very useful. For example, it can allow you to check the low frequency response of amplifiers and loudspeakers. Similarly, the higher frequencies are available for checking the upper response of power amplifiers and other analog circuitry. The generator has a 4-digit LED readout so you can set the frequen- cy exactly. The output frequency is selectable in four ranges, with a slight overlap between each: 0.1-10Hz; 10-1000Hz; 1-100kHz; and 100-500kHz. Presentation The styling of the new Digital Sine/Square Generator is similar to that of the 1GHz Frequency Meter (SILICON CHIP; Nov-Dec. 1987 & Jan. 1988) and the Capacitance Meter (May 1990). It is housed in a plastic instrument case and uses a 4-digit LED display behind a red perspex panel with a Dynamark label covering the lower half of the panel. It has two knobs for the range selection, two knobs for frequency setting (fine and coarse), and a knob for the output level. There is also a pushbutton ON/OFF switch, a miniature toggle switch to select sine or square wave output, and a BNC socket for the output terminal. Waveform synthesis So what's special about this new generator design? So far we've told you what it isn't. It isn't a Wien Bridge and it isn't based on conventional function generator circuitry. Incidentally, it does not produce the more exotic waveforms found on some function generators, such as triangle and sawtooth ramps. In our experience, these waveforms are seldom used and are provided simply because the circuit produces them rather than because they have any real use. Our new generator produces its sinewaves by a process which can Specifications Frequency Range 0.1 Hz-500kHz in four ranges : 0 .1-1 OHz; 1 0-1 OOOHz; 1-1 OOkHz; & 100-500kHz Output Waveforms Sine & square Harmonic Distortion Square Wave Rise Time Less than 0.1 % from 0 .1 Hz-50kHz; 0 .27% at 80kHz 1Ons Square Wave Fall Time 1 Ons Output Level Sine wave : variable from 0 -1.2V RMS Square wave: variable from 0-5V p-p Output Impedance 6000 nominal Load Impedance 6000 to infinity Protection Short circuit protected (indefinite) Display Accuracy ±2% + be called waveform synthesis or more accurately, "piecewise linear approximation". In this process, the circuit builds up the sinewave in little steps which are quite accurate in their absolute level but then we need filtering to remove the discontinuities due to the steps. The block diagram of Fig.1 shows the main components of the generator circuit. The key to the circuit is an up/down counter and a staircase generator. The up/down counter runs from O up to 9 and then back down again to 0, repeating the sequence continuously. The counter drives the staircase generator which produces one half of a sinewave (from trough to crest) 1 digit on the count from 0-9. Then, as the counter counts down from 9 to 0, the staircase generator produces the next half of the sinewave, from crest to trough. This process is continuous and the result is a sinewave approximation, with 9 steps from trough to crest, and 9 steps from crest to trough. You can see this stepped waveform in one of the oscilloscope photos accompanying this article. Naturally, before we can use this waveform, it must be filtered and this is done in a switched capacitor filter and a tracking RC filter. These two filters effectively remove all the switching hash associated with the waveform synthesis and VR2a ,VR3a SWITCHED CAPACITOR FILTER S1 : 1 : O.1HZ·1OOkHz 2 : 1OOkHz-SOOkHz - -TIMEBASE -.166.6ms 1 5410 LEVEL CONTROL FREQUENCY READOUT 55.55ms 2 Fig.1: the up/down counter controls a staircase generator which produces one half of a sinewave on the count from O to 9 and the other half on the count from 9 down to O. This signal is then filtered & fed to the output. The square wave signal is derived from the up/down counter circuitry. JULY 1990 17 COARSE ANE VR2b 500k LIN VR3b 1Ok LIN +5V 0.1+ gggg MAX VR4 5k 16 ------1 16 IC8 74HC390 11 4 IC9 4518 10 IC10 74LS192 (74HC192) 12 15 10 9 .,. +100 MASTER CLOCK OSCILLATOR VR6 100k FREQUENCY DISPLAY 4xHOSP5303 VR7 20k a ,, g 1 I I •/_Jc 12 CK 10 15VW TANT ,_, f d ,-, I I I I I_I 10 + T- COM OP 3,8 5 IC12 74C926 OIUL+ +5V COM DP 3,8 5 COM 3.8 A7 TIME BASE OSCILLATOR 16 B8 14 K· 15 R 10 31 1 R C 0 IC13 4017 4 24 13 E 5 0 11 LE 18 OS 6 .,. 'I' .,. +5V 1 16VW r· POWER 471l + 10 16VW+ S1 : 1 : 0.1Hz-100kHz 2 : 100kHz-500kHz OUT -1---+sv 1 16VW S2 : 1 : 0.1 Hz-1 OHz 2: 10Hz-1kHz 3: 1kHz-100kHz + eo----i . DIGITAL SIGNAL GENERATOR the result is a very clean sinewave which is fed to the output buffer and level control. Other features of the block diagram need not concern us now but they are included for completeness. They include the master clock generator, a number of divider stages to drive the up/down 18 SILICON CHIP counter, and the timebase and digital frequency readout circuits. Circuit details Now let's have a look at the circuit of Fig.2. ICl is the up/down counter referred to above. It is a 741S190 (or 74HC190) high speed decade counter which has 4-bit BCD outputs: QA, QB, QC & QD. These outputs are decoded by IC2, a 74HC42 BCD-to-decimal decoder. IC2 has 10 outputs, from O to 9, but we don't use the "O" output in this circuit. Because ICl counts in BCD (binary coded decimal), each successive output of IC2 goes low ( + 5V) for one clock period. 16 0.1+ 1 2 01! 16 34 11 LOAD +3 15 A 2 14 B QC 6 13 C 7 12 D 45 * 270k *3.3k * 82k 1 OD UPI DOWN 5 IC2 74HC42 10pF +10V * 10k *1k * 39k * 22k * 2.2k * 18k 56 EN 8 OA 3 OB IC1 74LS190 (74HC190) 15 10 9 23 * 47k 0.1 4.7 OFFSET ADJ~r---10k + 25VW .,. * 120k SUMMING AMPLIFIER 6 7 -10V 0.1 ~ 79 +5V * 33k 14 10 PR 09 IC6 11 CK 74HC74 08 * 10k CLR 7 13 DECADE DECODER CLOCK INPUT +5V *10k +5V 11 12 8 *1 % ~---------5v 0.1 10 STAIRCASE SINE WAVE SQUARE WAVE 0.1 SQUARE BUFFER 16 15 IC4 LMF100CCN 17 * 20k * 10k * 20k .,. 19 18 COARSE VR2a 500k LIN 20 +10V * 10k * 10k FINE VR3a 10k LIN OUTPUT 4.7 + 25VW-r -10V 22pF 22pF SOUA'RE S3a SWITCHED CAPACITOR FILTER (HOLE LOW-PASS) OUTPUT SINE S11 S2c ffi ffi 5 5 IN OUT GNO GND OUT B ELJc VIEWED FROM BELOW IN 1 ' j_ "! .,,; """I One of the crucial circuit functions is to change ICl 's mode from counting up to counting down, and so on. This is achieved by IC6, a 74HC74 dual-D flipflop. We use only one flipflop in this chip and it is clocked by the minimax output, pin 12, of ICl. So when ICl gets a clock pulse which would cause it to count S3b 11 TRACKING RC FILTER beyond its maximum count of 9 [ie, overflows), its minimax output goes high and toggles IC6 which then changes state at its Q output, pin 9. Pin 9 of IC6 is connected to pin 5 of ICl. When pin 5 is low, IC2 counts up; when it is high, ICl counts down. So IC6 is hooked into ICl to automatically change its LEVEL VR5 1k LIN SOUARi SINE .,. 10k SINE BUFFER Fig.2: ICl is the up/down counter shown in Fig.1. Its minimax output clocks flipflop IC6. When Q of IC6 is low, ICl counts up (0-9); when it is high, ICl counts down (9-0). ICl 's outputs are decoded by IC2 & summed by IC3 to produce a stepped sinewave. This waveform is then filtered by switched capacitor filter IC4 and the RC tracking filter. ICs 7-11 provide the timebase while ICs 12 & 13 drive the frequency display. JULY 1990 19 Despite the circuit complexity, the construction is straightforward. All the parts (except the mains switch) are mounted on two PC boards which are soldered together at right angles via edge connector pads. The completed assembly then fits inside a plastic instrument case. mode from counting up to counting down and so on. So we have seen how ICl & ICZ, together with IC6, count from Oto 9 and then back down again. Nine outputs of ICZ are coupled to IC3, an LM318 high speed op amp which functions as a summing amplifier, although the "O" output does play a part, even though it is not physically connected. It is IC3 and its associated resistor network which actually produces the stepped sinewave from the outputs of ICZ. Notice that the resistors connected to the nine outputs of ICZ reduce in value as they go from 1 to 9. For example, pin 2 of ICZ (the "1" output) has a total of 317Hl connected to it (270kfl + 47kfl), whereas pin 11 (the "9" output) has only 10kfl connected to it. Thus, when the (uncon20 SILICON CHIP nected) "O" output of ICZ is high, the circuit produces the trough (ie, the minimum peak) of the stepped sinewave. When pin 11 is high, it produces the crest (ie, positive peak) of the stepped sinewave. So IC3 produces a stepped sinewave at its output. Because the signal is summed from ICZ, the signal would normally have a DC offset of - 2.5 volts. This is because all the outputs of IC2 switch between OV and + 5V. This DC offset is cancelled out by feeding a DC signal of + 2.5V from the wiper of trimpot VRl to the non-inverting input of IC3. The waveforms shown in Fig.3 demonstrate how the sinewave is generated. The top waveform is that present at pin 3 of ICl , the QA output. It is half the clock frequency fed to pin 14 of IC1. The next 10 waveforms are those present at the decoded outputs of IC2. Now look down to the second lowest waveform which is present at pin 6 of IC3. This shows how the steps of the generated sinewave coincide with the pulses from IC2. Switched capacitor filter Another crucial factor in obtaining the high performacne of this circuit is the use of a National Semiconductor LMF100 dual switched capacitor filter. The beauty of this device is that it allows the design of a filter with variable cutoff frequency and that is just what is needed here. Consider that the hash to be filtered out of the sinewave output is essentially a square wave with a frequency 18 times higher (than the sinewave). And since the sinewave output ranges from 0.1Hz to 500kHz, the switching frequency (actually the clock frequency to ICl) will range from 1.8Hz to 9MHz. So what is needed is an effective filter which will track the oscillator frequency - a filter with a fixed cutoff frequency would be useless. This is where the LMF100 from National Semiconductor comes into the picture although even it cannot cover the whole operating range it covers the oscillator frequency range up to l00kHz. We don't plan to explain just how the LMF100 works in this article we just don't have the space. In essence though, it can be considered as a number of cascaded low pass filters in which the capacitors are varied by switching them rapidly in and out of circuit. This has the effect of varying the amount of capacitance in each of the filter stages and thereby causes the filter's cutoff frequency to track the clock frequency - just as we want. What actually happens is that IC4, the LMF100, is fed with a signal which is 3 times the clock signal fed to ICl, or 54 times (3 x 18) the ultimate sinewave frequency. This 54 times clock signal comes from IC7f, a Schmitt trigger buffer stage following IC9. RC tracking filter While the LMFl00 filter removes just about all the switching hash from the sinewave, some hash still remains and that is the reason for a further RC tracking filter. It consists of potentiometers VR2a and VR3a and a 4.7kQ resistor, along with the capacitors connected to S2c and Slf. The switches select the 2.2µF capacitor for the 0.1lOHz range, the .022µF capacitor for the 10-lO00Hz range, the 220pF capacitor for the 1-lO0kHz range and the lO0pF capacitor for the 100-500kHz range. VR2a & VR3a are ganged with VR2b & VR3b respectively. The latter control the frequency of the master clock oscillator. Thus, as the frequency of the generated sinewave varies, so does the the rolloff point of this passive RC filter. Output buffer Since the output of the RC tracking filter is essentially a high impedance, it needs to be followed by a high impedance buffer stage 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 OA. IC1 u u 1SLJ LJ LJ LJ LJ LJ IC2 LJ LJ LJ LJ LJ LJ LJ7J u~~□1N 7..______ co_uN_r_uP_ _ _ _ PIN6, IC3 L c□uNT o□wN n MINIMAX ,_ J IC1 __,I n '--------------'~-------------'ll ---..~_.,--...r-_,..___r-~...r--r--;-::;-..__...,_~--,, ~6 _J SINE WAVE SQUARE WAVE .____ _ ____.r Fig.3: these waveforms show how the stepped sinewave is generated. Each successive decoded output of IC2 goes low for one clock period as IC2 counts from 0-9, then from 9-0 & so on. These decoded outputs are summed by IC3 to produce the stepped sinewave (second from bottom). The square wave is derived from Q-bar of IC6. before being coupled to the output. This function is performed by IC5, Ql & QZ which together can be thought of as a power op amp with a gain of unity. D1 & D2 provide a small amount of bias to the output transistors, Ql and QZ, to ensure that crossover distortion is eliminated from the output. After all, there's not much point in generating a low distortion sinewave and then spoiling it in the buffer stage. Square wave generation So far we have not mentioned how square waves are generated by the circuit but in fact they come very easily, from the Q-bar output of IC6 (the same IC that generates the up/down control signal for ICl). Hence, IC6 produces a square wave which is always locked to the sinewave output from IC3. Toggle switch S3a selects either the sinewave signal from the buffer or the square wave signal from paralleled Schmitt trigger inverters IC7c, IC7d & IC7e which buffer the Q-bar signal from IC6. From there, the output signal goes to a lkQ level pot (VR5) and then to the output socket. Note that S3 is a double pole single throw (DPST] switch and that S3b (the second pole] appears to be doing nothing, switching between earth and earth! However, it does have a purpose and it selects the best earth point for the cold end of VR5, so that the output signal is free of extraneous noise, in either sinewave or square wave modes. Master clock IC7b, a high speed CMOS Schmitt trigger, is connected to function as the master clock oscillator. It is varied in frequency by two potentiometers in series, VR2b & VR3b, which function as the coarse and fine frequency controls. Depending on the range selected by Sl, the master clock oscillator is either 54 JULY1990 21 PARTS LIST FOR THE DIGITAL SINE/SQUARE GENERATOR 1 PCB, code SC04108901, 162 x 225mm 1 PCB, code SC04108902, 225 x 75mm 1 display mask film, 248 x 75mm 1 Dynamark front panel label, 248 x 42mm 1 grey plastic instrument case, 263 x 1 90 x 84mm 1 red perspex front panel, 250 x 75 x 2.5mm 1 2155 15V centre-tapped 1 A mains transformer 1 mains cord & plug 1 mains cord grip grommet 5 knobs 1 T0220 U-shaped heatsink, 25 x 27 x 34mm 1 DPDT toggle switch (S3) 1 1OOmm-length of 1 0mm heatshrink tubing 1 240VAC push-on/push-off switch (S4; DSE Cat. DSE P-7566 or Altronics Cat. S-1090) 1 6-pole 2-position rotary switch (S1; DSE Cat. P-7502 or Altronics Cat. S-3002) 1 4-pole 3-position rotary switch (S2; DSE Cat. P-7504 or Altronics Cat. S-3003) 1 BNC panel socket 40 Molex pins 4 HDSP5303 13mm red 7 -segment common cathode displays 2 metres of 0.8mm tinned copper wire 10 PC stakes 1 1 50mm length of medium duty hookup wire 550mm length of heavy duty hookup wire 3 machine screws, nuts and washers 4 self-tapping screws 1 solder lug Semiconductors 1 7 4HC190 or 7 4LS190 decade up/down counter (IC1) 1 7 4HC42 decade decoder (IC2) 1 LM318 high speed op amp (IC3) LMF1 OOCCN switched capacitor filter (IC4) LF351 FET input op amp (IC5) 1 7 4HC7 4 dual-D flipflop (IC6) 1 7 4HC1 4 hex Schmitt trigger (IC7) 1 7 4HC390 dual decade counter (IC8) 1 4518 dual decade counter (IC9) 1 7 4HC192 or 7 4LS192 decade up/down counter (IC10) 1 7 4HCOO quad NANO gate (IC11) 7 4C926 4-digit counter (IC12) 1 4017 decade counter (IC13) 5 BC338 NPN transistors (01 ,03,04,05,06) 1 BC328 PNP transistor (02) 2 7805 3-terminal +5V regulators (REG1, REG2) 1 7905 3-terminal -5V regulator (REG3) 4 1 N4002 1 A diodes (D3-D6) 2 1 N41 48 signal diodes (D1 ,02) Capacitors 2 1000µ,F 16VW PC electrolytic 1 1 Oµ,F 16VW PC electrolytic 1 1 Oµ,F 1 6VW low leakage electrolytic or tantalum 2 4.7µ,F 25VW PC electrolytic 1 2 .2µ,F 16VW PC electrolytic 3 1µ,F 1 6VW electrolytic 10 0. 1µ,F monolithic 1 .022µ,F metallised polyester 1 220pF ceramic A lkHz stepped sinewave as it appears at pin 6 of IC3 (0.2ms/div). The lkHz waveform after digital filtering by IC4 (0.2ms/div). The lkHz waveform after passing through the tracking filter (0.2ms/div). The sinewave output at 480kHz (timebase setting .03µs/div). The square wave response at lkHz (0.3ms/div). The square wave output at 90kHz (5V p-p; risetime l0ns). 22 SILICON CHIP IC7a, PIN2 R, IC13 1 1 2 1 1 1 1 OOpF ceramic 22pF NPO ceramic 22pF ceramic 12pF ceramic 1 OpF NPO ceramic 1OpF ceramic Potentiometers 1 500k0 dual gang PCBmounting linear pot (VR2) 1 1 OkO dual gang PCBmounting linear pot (VR3) 1 1kO linear pot (VR5) Trimpots 1 1 OkO miniature horizontal trimpot (VR 1) 1 5k0 miniature horizontal trimpot (VR4) 1 1 OOkO miniature horizontal trimpot (VR6) 1 20k0 miniature horizontal trimpot (VR7) Resistors (0.25W, 1 330k0 1 % 1 1 270k 1 % 3 1 120k 1 % 8 1 82k0 1 % 3 2 47k0 1 % 1 1 39k0 1 % 1 1 33k0 1 % 1 1 22k0 1% 9 2 20k0 1 % 2 5%) 1 8k0 1 % 15k0 1 % 1OkO 1 % 1OkO 4 .7k0 2 .2k0 2700 470 330 times the sinewave frequency (ie, up to 5.4MHz for a l00kHz output) or 18 times the sinewave frequen~y (ie, up to 9MHz for 500kHz output). IC8 and IC9 are dual decade counters set to divide by 100 so that the output of IC9 gives an overall division of 10,000. IC8 is a 74HC390 high speed CMOS counter to cope with the 5.4MHz master clock frequency for a sinewave output of lO0kHz and the 9MHz master clock frequency for the 500kHz output. IC9 is a standard 4518 CMOS counter which can easily cope with its maximum input clock frequency 90kHz (from IC8). Range switch SZb selects the clock signals for IC7f & IClO, from either the master clock, IC8 or IC9. IClO and ICl 1 act as a divide-by-3 circuit which is necessary when the LMFlO0 switched capacitor filter is in use. Otherwise, the divide-by-3 circuit is bypassed by Sle, at the input to ICl. _J .....___ ___.1 CK, IC12 LE, IC12 R, IC12 Fig.4: the counter circuit waveforms, IC7a produces a gating pulse to gate through pulses from the timebase to the clock (CK) input of counter IC12. The count is then latched (LE) and the counter reset (R). IC13 is then disabled by the high on its CE input until reset by the high from IC7a. CE, IC13 Digital display The 4-digit display circuit has the same fast update time for all the frequency ranges. This is achieved by having the display circuit count the "master clock divided by 100" output from IC8. The counter circuit requires its own fixed clock timebase, although two clock frequencies are required to cope with either the 0. lHzlO0kHz range or the 100-500kHz range. IC7a, another Schmitt trigger in the IC7 package, functions as the timebase oscillator with the two frequency settings selected by Sla. Trimpots VR6 & VR7 allow precise calibration of these frequencies. A 74C926 4-digit counter (IC12) is used to count and display the frequency, while IC13, a 4017 decade counter, is used to provide the necessary reset and latch enable signals. The way the counter circuitry works is illustrated by the waveforms of Fig.4. What happens is that the timebase oscillator from pin 2 of IC7a and the divided clock signal from IC8 are applied to the two inputs of NAND gate ICl la. This gates through a 166 or 55 millisecond portion of the divided clock signal, depending on the setting of switch Sla (see Fig.1). This gated signal is applied to pin 12 of IC12 which then counts it in its four decade counters. At the end of the timebase period, a short pulse is applied from pin 4 of IC13 to the latch enable input, pin 5, of IC12. This latches the contents of the four internal counters into the display registers so that they can be displayed by the LED readouts. Shortly after the latch enable pulse, another pulse is applied from pin 7 of IC13 to the reset input, pin 13, of IC12. This resets the four internal counters, ready for the next gated clock signal. IC13 is then stopped from further counting by the high signal from its pin 4 to pin 13 and it is reset the next time the timebase signal from IC7a goes high. IClla then gates through another 166 or 55ms period of clock signals to be counted. You can see the sequence of counter operation in Fig.4. The top waveform is the timebase signal from IC7a. The second waveform is the gated clock signal fi:om pin 3 of ICl la. The remaining three waveforms are the latch enable, reset and chip enable pulses, in that order. Power supply The supply uses a 15V centretapped transformer which feeds a bridge rectifier (diodes D3-D6) and two 1000µF electrolytic capacitors. The resulting ± 10V supplies provide power for the op amps, IC3 & IC5, and also for the 3-terminal regulators. There are two + 5V regulators (REGl & REG2) and one - 5V regulator (REG3). REG 1 is used to power most of the generator circuit while REGZ is used to power the LED display and IC12. The two separate positive regulators are used to ensure that the hash produced by the display counter circuitry is kept out of the sensitive generator circuitry. Next month we will conclude the description of this project with the construction and setting up details. JULY 1990 23