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Digital electronics has moved from the outskirts to the forefront of our hobby. Beres your chance to learn about or refresh your knowledge ·o f some of the basic elements of that technology. By JOSEPH J. CARR An Introduction to Digital Electronics You don't have to be too old to remember when digital electronics was the province of a few esoteric specialists who worked in forsaken realms of electronics. Everyone in those days "knew" that analog electronics was "real" electronics. But times changed; digital electronics eventually became easily accessible to all because of the introduction of integrated-circuit logic elements. The costs of digital technology have also dropped precipitously over the years. Originally, there was one fly in the digital ointment: price. This author can recall paying $5 for a NAND-gate chip in 1967 and nearly $14 for a 7490 BCD-output decade counter. Today the 7490 is less than $2 (and a great deal less in terms of 1967 dollars). Reliability has improved over the past two decades as well. At one time, a large digital project was unreliable by default. But today, chips hold up well and projects can be expected to last a long time. Copyright (c) Gernsback Publications, USA. Reprinted with permission from Popular Electronics, April 1990. 16 SILICON CHIP Even "green" chips, which by definition have no factory burn-in, perform as well as many highreliability devices. In this article we will take a look at the most fundamental building blocks of digital electronics: gates and flipflops. All larger digital circuits, whether a simple BCD counter like the 7490 or a largescale integration (LSI) microprocessor chip, ultimately boil down to a very few, different forms of digital-logic gates. We will learn about those basic-circuit elements below. Logic Families Digital-logic families are devices using the same technology and the same general circuit elements. They are designed so that it is easy to interface them using only electrical conductors (eg, wires and printed-circuit traces). The interfacing chore is thus eliminated because we don't need to worry about matching signal levels and . LJ o-----{>o----o B A LOW+ HIGH INPUT A OUTPUT B 0 1 1 0 INPUT A I I I I I I I I I I ouT[UT~ HH r-- 'LOWLJ LJ L_j D Fig.1: the inverter or NOT gate's schematic symbol is given in A. The circuit in B will mimic the gate's operation whose truth table is given in C. Typical waveforms for the device are shown in D. INPUT INPUT anything from - 15 to O volts for low, and O to + 15 volts for high. In general, one of two situations are standard in CMOS circuits. Either low is zero and high is + 5 volts (when TTL compatibility is needed), or low is a negative voltage and high is a positive voltage of the same value. The terms "positive logic" and "negative logic" sometimes confuse people who are just learning digital electronics. In positive-logic systems, a high will be a more positive voltage than a low. In negative-logic systems, a low will be more positive than a high. OUTPUT A B C 0 0 0 0 1 1 1 0 1 1 1 1 IN~UT--i__Jl_ I I I I I I I I I I INPUT B / I t I I I I I I I I OUi:"UT 1 1 I I I I L_]1_Jl_ D Fig.2: the 2-input OR gate (A) can be simulated by the circuit in B to yield the results shown in C. When operating in a circuit, it acts as shown in D. impedance values. The two modern digital-logic families consist of the transistor-totransistor logic (TTL) and complementary metal-oxide semiconductor (CMOS) devices. TTL devices are based on NPN/PNP bipolar transistors while the CMOS devices are based on field-effect transistors (MOSFETs). You can recognise CMOS devices by their "4xxx-series" part numbers (eg, 4049). TTL devices carry part numbers of 74xx (eg, 7490) or 74xxx (eg, 74161). Military (Mil -spec) TTL devices are sometimes seen in hobbyist parts suppliers as industrial surplus. Those devices carry the same number as the civilian version, except that the first "7" is replaced with a " 5" . In other words, a 5490 is a 7490 that's been drafted. Digital vs. Analog Digital electronics differs from analog electronics in the nature of the signals processed. In an analog circuit, a signal can have any value within a certain range. For example, suppose we have an operational amplifier connected for analog oper ation. Further, suppose that the output voltage can swing from - 12 to + 12 volts DC. In an analog circuit, the output voltage can take on any value between - 12 volts and + 12 volts; no values are forbidden . In digital circuits, on the other hand, the signals can take on only one of two permissible values - all Gates The most basic digital elements are gates. All digital circuits can be formed from only three such basic elements: the NOT gate, AND gate, and OR gate. Although these three gates can do it all, we also include the NOR, NAND and XOR gates among the basic elements. While discussing each gate, we'll show you its schematic symbol, an equivalent circuit made of switches that operate a lamp, and its truth table (in which 1 = high and o = low). Finally, we'll present a wavetrain example. other values are forbidden. Because only two values are permitted, we say those circuits are binary in nature. The two levels are often called 1 and O (or logical 1 and logical 0), true and false, or high and low. In this article, we will use high and low to denote the different states, except for a few cases where 1 and O seem particularly appropriate. The two families of digital devices use different voltage levels for high and low. For example, the TTL family uses + 2.4 to + 5 volts for high, and O volts to + 0.8 volts for low. In the CMOS family, on the other hand, it is possible to use Inverters Inverters, also called NOT gates, get their name from the fact that they produce an output that is the v+ :~c A .,. INPUT A INPUT B OUTPUT C 0 0 1 0 1 0 1 0 0 1 1 0 IN P l T 7 - - - 1 U L I , IN~UT I I I I I I I I I :in : LJnL.lJJ l ~ I I I I I I I I I I I I I 11 I I I II I I 11 I I I ouyu~ D Fig.3: the NOR-gate circuit symbol (A) is the same as the OR gate but with a circle at the output to indicate inversion. It is functionally equivalent to the circuit in B. Its truth table output is just the inverse of the OR gate's. Shown in D are some typical waveforms for the gate. NOVEMBER 1990 17 A ~ B~ C A B (output) is on (high) if either switch A or switch B is high. That's why they're called OR gates. A truth table for the OR gate is shown in Fig.ZC. What it says is that the output is low only when all inputs are also low. A high on any or both inputs produces a high output. The circuit action of those rules is shown in a practical form in Fig.ZD. Both inputs receive a series of pulses, and the change in output reflects the operation of the gate in response to those input levels. C '-o--<at>-i.,. v+-0~ IN~UT_Il__J7_ INPUT A INPUT B OUTPUT I I I I C I I I 0 0 0 I I 0 1 0 1 0 0 1 1 1 INPt iI I in ; n,I I I I I I I I I I I I I I I _J___u LJ.J I [J__ t 1, 1 11 1 1 1 OUTPUT C D Fig.4: the AND-gate's circuit symbol (A) should not be confused with the OR· gate's. A simple equivalent circuit can be constructed with two switches and a lamp, as in B. The device produces the truth table shown in C while typical waveforms are given in D. opposite of the input. A high input yields a low output and vice versa. The letter ''A'' is an expression that represents the input, so "A" can equal a high or a low. In like fashion, the letter ''B'' represents the output. An inverter is represented by a triangle on its side with a circle at the output (see Fig.lA). Whenever a circle appears at any lead (input or output) of a digital circuit it indicates inversion, as we'll see with some of the other gates. We can sometimes get better insight into a circuit's behaviour by looking at a simple equivalent circuit. In Fig. lB we have a simple DC circuit that represents the operation of an inverter. Switch Sl selects either a high signal (V + ) or a low signal (ground or O volts) as the input to the circuit. The lamp indicates the output - it's on for a high output and off for a low output. When the switch is in the high position, both sides of the lamp have the same potential so the lamp is not illuminated. That indicates a low output. When the switch is in the low position, the lamp receives both ground and V + so the lamp lights to indicate a high output. The truth table for the NOT gate is shown in Fig.lC. If the input is A and the output is B, we find that a low input produces a high output, and a high input produces a low output. This circuit action is shown in Fig. lD. In this case, the input is A while the output is called B or Abar. The line above the input or out18 SILICON CHIP NOR Gates The NOR gate is made by combining an OR gate with an inverter. (Note the circle on the output terminal in Fig.3A). The gate might be considered a NOT-OR gate. The NOR gate produces a low output if any or both inputs is high. An equivalent switch circuit for the NOR gate is shown in Fig.3B. As long as both switches are open, the lamp is on, but if either switch is closed then the lamp is turned off. The truth table for that type of circuit is shown in Fig.3C, which can be summarised by the following rules: the NOR output is high if, and only if, both inputs are low (ie, the output is low if any input is high). Those rules are presented in a more dynamic form in Fig.3D. put in logic notation indicates that the signal is the opposite of whatever the "unbarred" signal is. For example, if A is high, then Abar is low. We can use that notation to indicate the relationship between the input and the output: B = A-bar That is an expression used in Boolean algebra, which is the mathematics of digital logic. OR Gates An OR gate (Fig.ZA) produces a high output if at least one input is high. So if A, B, or both A and B are high, then the output is high. Another, perhaps simpler, way to put that is to say both inputs must be low to get a low output. Fig.ZB shows a simple equivalent circuit for the OR gate. The lamp AND Gates The AND gate (see Fig.4A) produces a high output if and only if both inputs are high. The AND-gate :~c A INPAUT__IL___fL INPUT A INPUT B OUTPUT C 0 0 1 0 1 1 1 0 1 1 1 0 I I I I I I INPUT B ii I I I I n LJ:f!liL!__ __!_l_.j I I I I ] I I I I I I I I I I II II I I I I I I OUTPUT C D Fig.5: here we present the NAND-gate circuit symbol (A) an equivalent circuit (B), its truth table (C), and some typical waveforms (D,). v + ~~ h ~ ✓"-o A B 0 0 -:- IN~uTSl__Jl_ INPUT A INPUT B OUTPUT C 0 0 0 0 1 1 1 0 1 1 1 0 INPUT B ouyuT I I I I I I I I I I I I i ~ I I I I nl_J_J_ i I _u I LJ I I I I I I I I -1lJ1fL_Jl_ tle or nothing to do with computers. Most flipflops have two outputs called Q and Q-bar. The Q output is the main output, while Q-bar is said to be a complementary output. That is, when Q is high, then Q-bar will be low, and when Q is low, then Qbar will be high. Also, when an input line on a schematic diagram is shown with a small circla at the flipflop body, then that input is active when low. Otherwise, the input is active when high. RS Flipflops The RS, or "Reset-Set", flipflop is Fig.6: the XOR-gate (A) requires a more complex equivalent circuit, as shown in B. It generates the unique truth table given in C. The waveforms in D are characteristic of its behaviour. are high. As in our previous cases, a dynamic example of those rules is given in Fig.5D. A XOR Gates A SET INPUT RESET o I ii 0 INPUT 0 OUTPUT OUTPUT 0 1 0 1 0 1 1 1 msALLOWEO NO CHANGE I I 1 0 Fig.7: the circuit for a NOR-logic RS flipflop is shown in A while its truth table is given in B. equivalent switch circuit is shown in Fig.4B. The lamp is on only if switch A and switch B are closed. The truth table of Fig.4C can be summarised as follows: The output will be low if either input is low (ie, the output will be high only if all inputs are high). Those rules are summarised by the timing diagram of Fig.4D. NANO Gates The NAND gate (see Fig.5A) is made by combining an AND gate with an inverter. An equivalent circuit is shown in Fig.5B; if either switch is open the lamp is turned on and it will only go off if both switches are closed. The rules of operation are given in the truth table (see Fig.5C) and can be summarised as follows: the output is high if one or both inputs are low, which is to say the output is low only if both inputs The last basic gate that we will consider is the Exclusive-OR (XOR). That gate (shown in Fig.6A) is a little unusual but it has a lot of different applications. An equivalent circuit for the XOR gate is shown in Fig.6B. The switching circuit has two SPDT switches cross-connected as shown. The truth table (Fig.6C) reveals some interesting behaviour: if both inputs are low, then the output is low. If both inputs are high, then the output is again low. If one input is high, and the other is low, then the output is high. In other words, a low output occurs anytime that both inputs are at the same level (regardless of whether they're high or low). The output goes high only when one input (but not both together) is high. That behaviour is displayed in Fig.6D. o I o SET INPUT RESET INPUT 0 0 NO CHANGE 0 1 1 I 0 1 0 0 I 1 1 1 OISALLOWEO OUTPUT OUTPUT B Fig.8: the circuit for a NAND-logic RS flipflop appears in A while B shows its corresponding truth table. Fig.9: a clocked RS flipflop can only operate when the clock input goes high. The circuit then behaves in the same manner as the circuit shown in Fig.BA. SET Flipflops Once an electronics buff progresses beyond an understanding of elementary digital-logic gates, it's time to tackle the next order of circuit organisation - flipflop circuits. A flipflop is a one-bit memory device made of basic gates, although it is rarely thought of as such in this day of 256KB and 1MB dynamic-memory chips. But flipflops are still commonly used in digital electronics, both in computers and in circuits that have lit- RESET INVERTER LOAD/TRANSFER INPUT Fig.10: the master/slave flipflop circuit consists of two clocked RS flipflops, designated here as A and B. The circuit is configured so that the outputs of A drive the inputs of B. The two clock lines are driven out of phase from a common clock, through the load/transfer input. NOVEMBER 1990 19 _r· _r INACTIVE ACTION HERE 0 0 CLR CLK CK 0 0 SET 1 ACTION HERE a 0 A Fig.11: in a level-triggered flipflop, the circuit action happens when the level is either high (positive-level triggering) as in A or low (negativelevel triggering) as in B. Edge triggering occurs if the circuit changes state when the input signal is in transition from either low-to-high (at the positive edge) or high-to-low (at the negative edge) as illustrated in C and D, respectively. a flipflop circuit that has two inputs: set and reset. When the reset input is made active, the Q output is forced low (if a Q-bar output is available, then it is forced high). The set input has just the opposite effect: an active input signal forces the Q output high and the Q-bar output low. There are two forms of RS flipflop: NOR-logic and NAND-logic. The NOR-logic RS flipflop circuits are configured with 2-input NORgates such as in the 7402 devices. The NAND-gate circuits are built using 2-input NAND-gates such as in the 7400 chips. The NOR-logic flipflop circuit is shown in Fig.7 A, while the truth table is shown in Fig.7B. The NOR logic circuit uses active-high inputs. In other words, a low on both inputs at the same time will result in no output change. But if either input is made high, while the other is low, then the result will be an outputstate change. Which state occurs depends upon whether it was the set or reset input that was made active. The condition of both inputs being simultaneously high is disallowed because the results will be unpredictable. The NAND logic circuit (Fig.BA) uses 2-input NAND gates instead of NOR gates to form a flipflop. They act just the opposite of NOR-gate flipflops (compare Fig.SB with Fig.7B). There are two RS flipflop chips available in the CMOS family of 20 SILICON CHIP B Fig.12: the D-type flipflop (A) is a 1-bit data latch. It will transfer the data on the D input line when the clock line switches high. The waveform timing· diagram (B) shows how the Q output switches with the D input and clock pulses. devices. The 4043 is a quad NORlogic RS flipflop ("quad" because four RS flipflops are in the same package). Similarly, the 4044 device is a quad NAND-logic RS flipflop. Clocked RS Flipflops One of the problems inherent in the design of the RS flipflop is that noise on the inputs can trigger an output transition. Also, the RS flipflop is asynchronous - it is not time-dependent and will operate whenever a valid input is applied. A solution to those kinds of problems is the clocked RS flipflop circuit of Fig.9. The two gates on the right form a NAND gate logic RS flipflop in the same manner as in Fig.BA. The inputs of this flipflop are controlled by the outputs of the other two NAND gates. As long as the clock input remains low, the outputs of both left gates are locked high, so the RS flipflop cannot operate. However, if ffii the clock-input goes high, then the inputs of the RS flipflop will respond to the inputs applied to the set or reset inputs. Master-Slave Flipflop The so-called "master-slave" flipflop is shown in Fig.10. This circuit consists of two clocked RS flipflops, A and B as shown. The circuit is configured such that the outputs of the left flipflop drive the inputs of the right one. The two clock lines are driven out of phase with one another but from a common clock line, now called the load/transfer (or LIT) input. If the LIT line is high, then the clock of the A flipflop is low and the B one is high. Under that condition, B is active and A is inactive. Whatever levels appear on the outputs of A are automatically transferred to the outputs of B by virtue of CLK2 being high. But when the LIT line goes low, B is disabled (but its outputs remain the same) ffmi SET 0 0 OISALLOWEO 0 1 0 1 0 1 1 NORMAL FOR CLOCKED OPERATION 0 CLK 0 SET 1 J K 0 0 0 1 1 0 1 1 CLK OUTPUT 0 OUTPUT Q CLOCKm l NO CHANGE T1 T2 T3 T4 I I I I I 0 1 FLIPS TO THE OPPOSITE STATE ou1fUT / I I I T5 T6 I I i I I I:j C Fig.13: the JK flipflop (A) can be operated in either of two modes - direct and clocked. The logic truth table for the direct mode is shown in B while the truth table for clocked operation is shown in C. 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LTD. 14B MAXWELL STREET, TURRAMURRA N.S .W. 2074 TELEPHONE: (02) 988 3865 FAX: (02) 988 3861 Fo1 = F/2 Fo2 CLOCK = F/4 Fo3 CLK WITH F/8 Fo4 = F/16 03 02 PULSES = CLK CLK CLK FREQUENCY F A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLOCK 01 02 L 03 04 Fig.14: shown in A is a 4-bit binary counter made from four JK flipflops. The timing diagram for the circuit is shown in B. Note that each successive stage divides the input frequency by 2. and A is enabled. Any changes on the S and R inputs are reflected on the Qt/Qt-bar outputs of A. When the LIT line goes high again, those new levels are transferred to the outputs of B. The master-slave flipflop is used where noise or synchronisation is a problem. In some flipflops, we see a difference between various types of clock triggering. Figs.11A & 11B show the difference between positive and negative-level triggering. In level triggering, the circuit action happens when the level is either high (positive-level triggering) or low (negative-level triggering). Edge triggering occurs when the input signal is in transition from either low to high (called positiveedge triggering) as in Fig.11C, or high to low (called negative-edge triggering) as shown in Fig.11D. Type-D Flipflops The D-type flipflop , also sometimes called a 1-bit data latch, is a digital circuit (Fig.12A) that will transfer the data on its D input line to the Q output when the clock 22 SILICO N CHIP (CLK) input goes high. Thus, the Dtype flipflop is said to "latch" the data on the D input for one clock cycle. Fig.12B summarises the operation of the D-type flipflop. When the clock pulse goes from binary O to binary 1, the latch stores the input state (ie, if D is high, then Q will go high; if Dis low, then Q will switch low). Note also that if the clock input remains high, the Q output will simply follow the signal applied to the D input. Examples of D-type flipflops include the 7474 dual edge-triggered TTL flipflop and the 4013 CMOS device. JK Flipflops The JK flipflop (Fig.13A) can be operated in either of two modes: direct and clocked. This device has five inputs and two outputs. The set and clear (CLR) inputs are similar in operation to the set and reset inputs on a basic latch. The J and K inputs are synchronous inputs and are similar to the set and reset inputs of a clocked flipflop. "J" means set while " K" means reset. Finally, the device also has a clock input and the standard Q and Q-bar outputs. The set and clear inputs are asynchronous in nature. They are normally held high and in that state have no affect on the operation of the flipflop. However, to set or reset the flipflop as you would an ordinary latch , momentary low signals are applied as required. For example, to reset the flipflop, a binary O would be applied to the clear input. The Q output would then go to the binary O state. The logic truth table for the direct mode of operation is shown in Fig.13B. When both clear and set are low, the JK flipflop does not know what to do , so that state is disallowed. The results are unpredictable if this occurs, so avoid that combination of inputs. When the clear input is low and the set input is high, then the Q output immediately goes low and the Q-bar output is high. However, when the clear input is high and the set input is low, the opposite action takes place: Q = high and Q-bar = low. Finally, note the action when both clear and set are high: the JK flipflop is set up for clocked operation and a different set of rules applies. Note also that the clear and set inputs override the J, K and clock inputs. Their main application is to preset the flipflop to one state or the other prior to another operation taking place. Now let 's consider the synchronous inputs. The truth table for clocked operation of the flipflop is shown in Fig.13C. The JK flipflop is a negative-edge triggered device; ie, the circuit's output transitions only occur during high-to-low transitions of the dock (CLK) line. If both the J and K inputs are low, then there will be no change in the output state during clock transitions. But if J is low and K is high, then a clock transition forces Q low and Q-bar high. Similarly, when J is high and K is low, the opposite occurs: Q goes high and Q-bar goes low. If both J and K are high, the Q output will flip to the opposite state when the negative-going clock transition occurs. A depiction of that is shown in Continued on page 93 list for the meter. Considering all its features, the price is a bargain at $199.50. You can get yours from Altronics in Perth or one of their distributors. Dual DACs in a single chip This series of new ICs from Analog Devices provides two digital-to-analog converters (DAC) in a single 24pin DIL or surface mount package. Having 12-bit resolution, the AD7237 and AD7247 each contain their own internal reference and can be loaded either serially or in parallel, depending on which device. With linking options, the output voltage can be changed to one of three ranges: 0 to +5V, 0 to +lOV or ±5V. Introduction to Digital Electronics - from p.22 clock pulses and the resulting outputs are shown in Fig.14B. Fig.13D. There it would appear that the input frequency is being divided in half. At time T1, the clock is positive-going so no change occurs. But at time TZ, there is a negative-going change, so the output snaps from low to high. The next negative-going transition occurs at T4, so the output line snaps low again. The result is that two input pulses (A and B) must be applied to the clock line to create one complete output pulse, therefore: fm = 2fout If JK flipflops are connected in cascade, as in Fig. 14A, their outputs form a binary division chain. In the 4-bit case shown, the input frequency of the clock is f. The frequency at Ql is f/2, at QZ it is f/4, at Q3 it is f/8, and at Q4 it is f/16. An example series of Conclusion Output accuracy is guaranteed to ±1 LSB. The power dissipation is 165mW from a 15V supply and the output buffering amplifier can provide a 10V output swing across a ZkQ load. ANTRIM TOROIDAL TRANSFORMERS Logic gates and flipflops are very useful electronic devices. Clearly understanding the rules governing each one allows the experimenter to use them in both traditional and non traditional circuit applications. By using your imagination, you will be able to solve a remarkable variety of electronics problems. Footnote: readers who want a more detailed course on Digital Electronics should refer to the 10part series entitled "Digital Fundamentals" by Louis Frenzel which was featured in the November 1987 to September 1988 issues of SILICON CH IP. For further information, contact the distributors for Analog Devices, NSD Australia, 205 Middleborough Road , Box Hill, Vic 3128. Phone (03) 890 0970. E-1 LAMINATED POWER TRANSFORMERS PCB mount ex-stock in sizes from 2.5VA to 25VA with secondary voltages from 2 x 6V to 2 x 20V. Triple output models also available for logic circuits. Chassis mount manufactured to order in sizes from 2.5VA to 1 KVA in E-1 and C core. PCB MOUNT STOCK RANGE QUALITY TOROIDAL POWER TRANSFORMERS, MANUFACTURED IN U.K. NOW AVAILABLE EX-STOCK AT REALISTIC PRICES. General Construction We are the largest ex-stock supplier of toroidal power transformers in Australia. Our standard range consists of the U.K. manufactured ANTRIM range in 10 VA sizes from 15VA to 625VA. All have a single 240V primary and dual secondary windings ranging from 2 x 6V to 2 x 55V. Our local manufacturing facilities supplement this range by manufacturing specials to order. Models are available from stock to suit most project kits. Comprehensive data sheets are available on request. Enquiries from resellers and manufacturers are welcomed. Prices are extremely competitive and generous trade discounts apply for quantity. CHASSIS MOUNT TO ORDER HARBUCH ELECTRONICS PTY LTD 90 George St .. HORNSBY NSW 2077 Phone (02)476-5854 NOVEMBER 1990 93