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Special project •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• This new colour TV pattern generator produces seven separate paUerns:checkerboard, crosshatch, dot, greyscale; white raster, red raster & colour bars. It will enable you to set your TV's convergence & purity for the best possible pictures. 16 SILICON CHIP colour pattern generator is an essential service tool for the TV serviceman since it provides known and standard patterns. On a well adjusted set, each pattern will be close to perfect, while on a poor set the patterns will be far from satisfactory. As a service aid, the pattern generator is invaluable for tracking down faulty circuit operation. The colour bar pattern is shown on virtually all television circuit diagrams as a standard staircase waveform. By comparing the expected waveforms with those found in the TV set when fed with the colour bar signal, it is often possible to determine the faulty section. Once the set is operating, the other patterns can be used to set and check the convergence and purity, and to make fine adjustments to optimise the overall performance. With the checkerboard pattern for A example, the frequency response of the video stages can be checked. When there is a poor high frequency response, the black and white edges of the pattern are smeared. The crosshatch pattern comprises 12 horizontal lines and 14 vertical lines. It is useful for adjusting picture geometry; ie, setting the correct height and width and minimising pin cushion distortion. Most important of all, the crosshatch pattern can be used for dynamic convergence adjustments. On a poorly converged set, the white lines will splay into red, blue and green lines at the edges of the screen. Similarly, the dot pattern, which is derived from the crosshatch pattern, is used for static convergence adjustments. On a poorly converged set, each dot will actually consist of blue, red and green dots which only roughly coincide instead of producing a perfect white dot. The white and red rasters are for ••••••••••••••••••••••••• purity adjustments. On sets with purity problems, the white raster (screen) may have blotches of red, blue or green. This may indicate the need to degauss (ie, de-magnetise) the metalwork around the picture tube. The generator produces the standard colour bar chart with colours from left to right: white, yellow, cyan, green, magenta, red, blue and black. The greyscale pattern is simply the colour bar chart with the chrominance signal switched off. This is not strictly a perfect grey scale since the luminance changes do not increment linearly from black to white. However, the resulting greyscale pattern can be used for setting up brightness and contrast. It can also be used to check for colour tinting which can occur with changes in brightness level. a •• e. Main features Despite the circuit complexity, the Colour TV Pattern Generator is very easy to build since virtually all the parts are mounted on a single PC board. An onboard RF modulator provides an output on channel 2 & there is also a direct video output available. The SILICON CHIP Colour TV Pattern Generator is housed in a plastic instrument case and is powered from a mains plugpack. The output is composite video or via an RF modulator set to channel 2. A rotary switch selects the patterns while a toggle switch selects either the greyscale or colour bars. All the pattern signals, sync and blanking are locked to a 4MHz crystal oscillator. This means that there is only one setting up adjustment and everything will remain in lock for the life of the instrument. Block diagram The circuit for the colour pattern generator is quite complicated with Build a colour TV pattern generator By JOHN CLARKE NOVEMBER 1991 17 I ◄ •• •• •• •• These four photographs show some of the patterns that are generated by the Colour TV Pattern Generator. They are, from top: checkerboard, greyscale bars, crosshatch & dot. In addition, the instrument can generate a colour bar pattern & white & red rasters for purity adjustments. its 16 ICs and all the interconnections. The block diagram of Fig.1 should be a help in understanding the circuit operation. We'll start at the top left-hand corner of the block diagram which shows the 4MHz crystal oscillator (ICla). This feeds a divide-by-16 circuit (IC2a, IC3, IC5a & IC6a) which produces the vertical crosshatch lines. These are a string of pulses 0.25µs long occurring every 4µs. A second divide-by-16 circuit (IC4, IC6b, IC5b & IC13a) provides the horizontal sync pulses which are 4µs long every 64µs . The frequency is therefore 1/64µs or 15.625kHz which is the standard line frequency. The same divide-by16 circuit also produces the horizontal blanking signal (lOµs pulses occurring every 64µs) and the vertical checkerboard signal (a square wave Bµs high and 8µs low). A divide-by-26 circuit (IC7a, IC5c, IC6c, etc) provides the horizontal crosshatch signal (64µs pulses occurring every 1.66ms). Note that strictly speaking, the division ratios quoted here are not precisely associated with the ICs mentioned but overall, the divisions are correct. The vertical and horizontal crosshatch signals are fed via NOR gate IClOa to produce the crosshatch pattern and through NAND gate IC9a to derive the dot pattern. A final divide-by-12 circuit (IC7b, ICld, IC8c, IC8d & ICZb) gives the vertical sync and vertical blanking signals. The repetition rate of these signals is very close to 20ms which is the standard field period. The blanking period is 1.66ms while the vertical sync period is 256µs. The horizontal checkerboard signal is also derived from this divideby-12 block. The horizontal sync and vertical sync waveforms are mixed together by OR gate IClDb to provide the composite sync signal. This is then applied to the colour encoder (IC16). Similarly, the horizontal and vertical blanking signals are mixed (by IC9b, IClOc & IClOd) to provide the composite blanking signal which is then fed to the colour encoder. The blanking signal is also mixed with the checkerboard, crosshatch or dot signals when required. The red and white raster, colour bars and grey scale are selected by the circuit blocks marked "bar select" and "preload red/white select". These two circuit blocks control the bar clock (IC14 & IC9d) and a down counter (IC15) which drives the red, blue and green inputs of the colour encoder (IC16). Note that the waveforms on the block diagram are all shown with the pulse going positive. This is done for clarity. The actual circuit waveforms, however, may be inverted to this. The colour bar video waveform produced by the pattern generator is shown in Fig.2. Circuit details Fig.3 shows the full circuit details. Most of the ICs used are high speed CMOS devices, necessary because of the 18 SILICON CHIP X1 4MHz _rC> """[_ ·4MHz CRYSTAL OSCILLATOR IC1a ~ +16 · Ic2a ,IC3 , IC5a ,IC6a --< ~ +16 IC4,IC6b, IC5b,IC13a - N ·I- - • 26 IC7a,IC5c,IC6c, IC8a,IC8b IC7b,IC1 +12d,IC8c, IC8d ,IC2b HOR IZONTAL ~ CROSSHATCH J__Jl_ -- 64~ 1.6ms 025y 4us VERTICAL CROSSHATCH HORIZONTAL CHECKER VERTICAL CHECKER I' JU1 8ltl XOR GATE IC11a 16us ~ 10~-64us - HORIZONTAL BLANKING '\ / -n1 Jl__J]_ POrrr64~ BAR SELECT S2a POSITION 6 IC9c,IC11 b, .IC13b RESET '-- BAR CLOCK IC14,IC9d I CLO;,K DOWN COUNTER IC15 -- RED GREEN --- '-- AND GATE IC9• ,,------ DOT CROSSHATCH j SWITCHING IC12a,b,c S2a POSITIONS 1,2,3,4,5 CHECKER , HATCH OR DOT BLANKING MIXER IC9b ,IC10c,IC10d HORIZONTAL SYNC PRELOAD RED/WHITE SELECT S2b NOR GATE IC10a VERTICAL SYNC ~ VERTICAL BLANKING ___L__J_ -ll:6us20ms • I SYNC MIXER IC10b INVERTED COMPOSITE SYNC CSYNC l CBLANK COLOUR ENCODER IC16 COMPOSITE BLANKING I COMPOSITE VIDEO OUTPUT TV MODULATOR ---Oou'VruT BLUE ~x~~ ~ VIDEO ~ OUTPUT 8.86MHz Fig.1: this block diagram shows the main circuit functions of the pattern generator. ICla & its associated 4MHz crystal form a crystal oscillator & this drives a number of divider stages & logic gates to derive the crosshatch, checkerboard & dot signals, & the horizontal & vertical sync signals. The red and white rasters, colour bars and grey scale are selected by the circuit blocks marked "bar select" and "preload red/white select". These two blocks control up/down counter IC15 which in turn drives the colour encoder (IC16). (IC6b) to produce the horizontal sync required high frequency waveforms. NAND gate ICla functions as the pulses. Note that the clock inputs of IC3 c:::ystal oscillator. One input is tied high so that the gate operates as an and IC4 are tied together so that all inverter. It is biased by a l0MQ resis- the Q outputs of these two dividers change state at the same time - giving tor and shunted by the 4MHz crystal. ideal synchronous operation. The 82pF capacitor at pin 4 and the The horizontal sync pulses are 4~ts 33pF capacitor at pin 6 provide corwide and occur every 64µs. The horirect loading for the crystal. The 4MHz square-wave signal from zontal blanking signal also occurs ICla is fed to IC2a which is a 74HC74 every 64µs but needs to be a 10µs D-type flipflop, connected to divide pulse rather than 4µs. To arrive at by 2. The resulting 2MHz signal is this, we can get an 8µs pulse at the then fed to the clock input of IC3 , a right repetition rate from the output 74HC161 4-bit synchronous binary ofNAND gate IC6b. IC13a, a 74HC74 D counter. flipflop, is used to extend the 8µs pulse to l0µs by taking .a further sigSignals from IC2a and IC3 are then fed to NAND gate IC6a and NOR gate nal from the Q3 output of IC3 . IC5a to provide the vertical crosshatch It works like this. Initially, when waveform. . the preset input at pin 4 ofIC13a goes low, the Q-bar output at pin 6 also The CARRY output of IC3 is fed to IC4, another 74HC161 4-bit synchro- goes low. This follows the output of nous counter. IC3's Q4 output and IC6b. Now when IC6b goes high again IC4's Ql , Q2 & Q3 outputs drive NOR after 8µs, the Q-bar output of IC13a gate IC5b and a 3-input NAND gate remains low until the clock input at pin 3 goes high 2µs later. Thus, we have the required l0µs horizontal blanking signal. The lkQ resistor and lO0pF capacitor at the preset input of IC13a provide a slight signal delay to prevent a "race" condition between the Q-bar output '.m d the clock input. Divide-by-13 The Q4 output of IC4 is used as the clock for the following divide-by-26 circuit consisting of IC7a, IC5c, IC6c, IC8a & IC8b. IC7a is one half of a 74HC393 dual 4-bit binary counter. Its Ql, Q3 & Q4 outputs are connected to IC6c, a 3-input NAND gate. When all three outputs go high after a count of 13, pin 8 ofIC6c goes low. This sets a flipflop consisting cross-coupled NAND gates IC8a & IC8b so that pin 8 of IC8 goes high and IC7a is reset. IC5 c, & 2-input OR gate is connected so that the clock input to IC7a is inverted. At the next high going clock pulse to IC7a, the output of IC8a (pin 11) goes high and pin 8 of IC8b goes low to release the reset on IC7a. IC7a is now ready to count on the next negative edge of the clock input. The reset signal for IC7a lasts for one half clock cycle or 64µs and this NOVEMBER 1991 19 1V PEAK -----,--W:.:.:H.::.:ll.:.E---l WHITE z ;:: c.., ~a: "' ffi a: w :l "' DV BLACK ....._____ 10-CYCLE COLOUR BURST LINE SYNC . PULSE Fig.2: this diagram shows the standard colour bar video waveform produced by the pattern generator. Note the leading line sync pulse & colour burst signals. becomes the horizontal crosshatch signal. Divide-by-12 The divide-by-12 circuit consists of IC7b, IC1d, ICBc, IC8d & ICZb. IC7b, the other half of the 74HC393 4-bit binary counter, derives its clock signal from the horizontal crosshatch; ie, the reset signal at pin 12 of IC7a. IC1d is a 2-input NANO gate which monitors the Q3 & Q4 outputs ofIC7b. On the count of 12, both inputs to IC1d are high and its pin 11 output goes low. This causes the pin 6 output of ICBd to go high and reset IC7b. When the clock input to IC7b subsequently goes high, pin 11 ofIC8a goes low and pin 3 of IC8c also goes low. The resulting output from IC8c is a 1.66ms pulse occurring every ZOms. This is the vertical blanking signal. IC2b is a 74HC74 D-flipflop which is used to delay the signal at pin 6 of IC8d by 256µs. This is necessary as will become clear in a moment. To get the 256µs vertical sync pulse, we need to cut short the length of the vertical blanking period. This is done using NOR gate IC5d which monitors the Q3 & Q4 outputs of IC7a. IC5d's output goes to NANO gate IC1b which also picks up the Q output of IC2b. The output of IC5d goes high at the beginning of the vertical blanking period and low 512µs later. Thus, the output of IC1b goes low 256µs after the start of the vertical blanking period (due to the IC2b delay period) and high 512µs after the start of the vertical blanking. This means that the vertical sync signal after inverter IC1c is high for 256µs every ZOms. This gives the desired timing of the vertical sync pulse with respect to the 20 SILICON CHIP vertical blanking pulse. The vertical sync at pin 3 of IC1c is combined with the horizontal sync at pin 4 of IC5b using 2-input NOR gate IC10b. This gives an inverted composite sync suitable for the TEA2000 colour encoder, IC16. Similarly, the vertical blanking at pin 3 of IC8c is combined with the horizontal blanking at pin 6 of IC13a by NAND gate IC9b to provide the composite blanking signal. The final composite blanking signal at the output of NOR gate IC10d (wired as an inverter) includes the checkerboard, crosshatch and dot patterns, if selected. The horizontal and vertical crosshatch signals are combined in NOR gate IC10a to obtain the crosshatch pattern and combined in NANO gate IC9a to obtain the dot pattern. The vertical checkerboard signal from Q2 ofIC7b is combined with the horizontal checkerboard signal at the Q1 output of IC4 using XOR gate IC11a. The outputs of IC9a, IC10a & IC11a connect to CMOS switches IC12a, IC12b & IC12c. The CMOS switch outputs are then commoned and connect to the pin 3 input of IC10c. The CMOS switches are controlled by rotary selector switch S2a. Normally, the control inputs of the CMOS switches are held at OV via 10kQ resistors. When a CMOS switch input is pulled high by rotary switch S2a, the corresponding pattern (checker, crosshatch or dot) is selected and fed through to IC10c. Colour patterns Positions 4 & 5 of rotary switch S2 are the white and red raster patterns respectively. These are produced by applying the white and red codes to IC16, the colour encoder. This is done by pulling two or more of the colour inputs (1, 2, 3, 4, 5 & 18) high (ie, to +5V). When all the colour inputs are high, the colour generated by IC16 is white. When only the red inputs (pins 1 & 18) are high, the colour generated is red. IC15 is used to generate the voltage levels for the blue, red and green inputs of IC16. It is a 74HC193 4-bit presettable, up/down counter which is wired to count down only. Only the three least significant outputs are used, Q1, Q2 & Q3. The A, B & C inputs are the preload inputs and control the Q1, Q2 & Q3 outputs respectively when the Preset Enable (PE) input at pin 11 is low. IC13b is a D flipflop which is clocked by the Q1 output ofIC4 while its CLR (clear) input, pin 13, is controlled by gates IC9c & IC11 b. IC9c receives the horizontal blanking signal at pin 4 and its pin 5 input is normally tied to OV with a 10kQ resistor. IC9c's output at pin 6 is thus normally high except when switch S2a is in position 6. Exclusive-OR gate IC11 b is connected as an inverter so that the CLR input of IC13b is normally low. When the clear input is low, the Q output ofIC13b is also low and so the IC15 down counter is preloaded with the voltage levels set at its A, B & C inputs. When the white pattern is selected (S2b at position 4), the A, B & C inputs of IC15 are all at +5V. This preloads the Q1, Q2 & Q3 outputs high and so IC16 is set to produce a white screen. When S2b is in position 5, the A and C preload inputs are pulled to OV and the B input remains high. This selects a low Q1 output for the blue inputs, a high Q2 output for the red inputs and a low Q3 output for the green inputs. Thus, IC16 produces a red screen. Colour bars When switch S2a is set to position Fig.3 (right): most of the ICs used in the circuit are high-speed CMOS devices to give the necessary frequency response. The device numbers can be directly related to the major circuit blocks shown in the block diagram (Fig.1). l VERTICAL CROSSHATCH +sv, ,41 74HC02 · • 11 • 31 ¥" 10 '::' . 10 10k 1_1)_ +sv · • HORIZONTAL ICROSSHATCH +5V ~ - - - - ~ - + 5 V- 33pFI 74HCOO +5V ◄ • , • +5V • .,. 1§. ' +5V +5V IC12c 1 PE· __ 1 2ICK ' S2a hH .~~k. IC15 74HC193 t ' 'I 021 2 ) ) ) ) ' I> S3 T l!! • ~ ·1 ~ 5.6pF.r 1 IRED qOLU 117 Ol 5.6pF! VC1 2·30pF IC16 TEA2000 t 12 ,04111 COMPOSITE BLANKING 330pF SYNC BLANK 16 COMPOSITEl10 SYNC HORIZONTAL SYNC VERTICAL SYNC HORIZONTAL BLANKING COLOUR 10k .,. IC11a 74HC86 IC4 74HC161 • • e e e • e • • 7 1CEP HORIZONTAL CHECKER 3x1N4148 > ,~ T 031 6 Ill l!.4 S2: PATTERN 1 : CHECKER 2 HATCH 3 DOT 4 WHITE 5 RED 6 BARS 121- 03 IC3 74HC161 • • e e e e e e e 1~ ·IC7a 74HC393 36k 11 12VAC PLUG-PACK 14 470 VIEWED FROM I +5V • • · 11 I 16VWT , 7'\ ~ _ .. Et:__:} C 01 BC337 +12V LED1 VERTICAL BLANKING ,i112 ~ • .. +0.6V IIN .,. o.1 I 680'1 1our, ~ GNO 02 -~- 13 JIJ RF OUTPUT _+5V .,. ~VIDEO OUTPUT mu _DUT _ 400mW -v~~!ff2E3 ·v+ 12 .,2v '~"' GND .,. 04 IC7b COLOUR TV PATTERN GENERATOR 01.:r POWER 8 19 04-113- UicK >--L---------------------------------------------------------------------------------J ~ co co ,_. ,_. :i:, tll t'l ~ ~ -r·· ~ 100 16VW 82pFI +5V. 10M; PARTS LIST 1 plastic instrument case, 205 x 158 x 62mm 1 PC board, code SC02210911, 175 x 142mm 1 Dynamark front panel label, 192 x 55mm 1 12VAC plugpack 1 4MHz parallel crystal (X1) 1 8.86MHz PAL TV crystal, 22pF series load (X2) 1 2-pole 6-position rotary switch (S2) 2 SPOT toggle switches (S1, S3) 1 5mm LED bezel 1 knob 1 RCA panel socket 1 cord grip grommet 1 VM416/A2E3 video modulator 1 3-metre length 0.8mm tinned copper wire 1 500mm-length 8-way ribbon cable 12 PC stakes Semiconductors 3 74HC00 quad 2-input NANO gates (IC1 ,IC8,IC9) 2 74HC02 quad 2-input NOR gates (IC5,IC10) 1 74HC10 triple 3-input NANO gate (IC6) 2 74HC7 4 dual D flipflops (IC2,IC13) 1 74HC86 quad XOR gate (IC11) 2 74HC161 4-bit synchronous counters_(IC3,IC4) 1 74HC 193 preloadable 4-bit up/down counter (IC15) 6, the blanking signal passes through IC11b to the CLR input ofIC13b. Thus, IC13b's Q output goes low during the blanking interval and high after the clock input goes high. The clock input to IC13b is from the Q1 output of IC4 and occurs 6µs after the horizontal blanking pulse from IC13a. Thus, the Q output goes high which releases the preset enable from IC15. The high Q output of IC13b also pulls up pin 4 of IC14, a CMOS 555 timer, which allows it to start oscillating. The 5.6kQ and lOkQ resistors at pin 7 and the associated 220pF capacitor set the frequency of the oscillator to about 255kHz. 22 SILICON CHIP 1 74HC393 dual 4-bit counter (IC?) 1 74HC4066 quad analog switch (IC12) 1 7555 CMOS timer (IC14) 1 TEA2000 colour encoder (IC16) 178123-terminal 12V regulator (REG1) 1 7805 3-terminal 5V regulator (REG2) .1 BC337 NPN transistor (01) 1 5mm red LED (LED1) 4 1N4002 1A diodes (D1-D4) 5 1N914, 1N4148 switching diodes (D5-O9) 1 6.8V, 400mW zener diode (ZD1) Capacitors 1 470µF 25VW PC electrolytic 2 470µF 16VW PC electrolytic 1 100µF 16VW PC electrolytic 2 1µF 16VW PC electrolytic 10 0.1 µF monolithic 2 .01 µF ceramic 1 330pF ceramic 5% tolerance 1 220pF polystyrene 2 100pF ceramic 1 82pF ceramic 1 33pF ceramic 2 5.6pF ceramic 1 2-30pF trimmer Resistors (0.25W, 5%) 1 10MQ 1 36kQ 1% 9 10kQ 1 5.6kQ 1 2.2kQ 31kQ 1 910Q 1% 1 680Q 1 470Q 1 390Q 1 330Q 0.5W 1 100Q The oscillator output at pin 3 is gated via IC9d which allows the signal to pass through to the clock input of IC15 when its pin 10 input is high. Normally, this input is held high via diodes D5, D6 & D7 which connect to the Q1, QZ & Q3 outputs of IC15. IC15 thus begins counting down, starting with Q1, QZ & Q3 high (ie, at +5V) and ending with all the Q outputs at ground. The intermediate counts, where there is a mix of high and low values at the Q outputs, provide the different colours in the colour bar pattern. When all the Q outputs are at ground, the colour is black and the cathodes of D5, D6 & D7 go low. The clock signal to IC15 is thus disabled and so the black signal from IC16 continues until the next blanking period. Note that the design provides extended white and black colour codes to IC16 to allow for the overscanning of the picture tube. Colour encoding We have already mentioned IC16, a Philips TEAZ0O0 colour encoder. It only requires the sync and blanking signals to be applied to its pin 16 & 17 inputs to produce the requisite PAL colour signal. To achieve this, the colour IC uses an 8.86MHz crystal to generate the 4.43MHz colour burst and chrominance information. A ramp generator, which operates in synchronisation with the composite sync, is controlled by the RC time constant of the 36kQ resistor and 330pF capacitor at pin 15. This time constant controls the position of the colour burst signal after the composite sync signal. The 1kQ and 910Q resistors at pins 7 & 8 set the luminance level for the composite video output at pin 6. Pin 10 contains the chrominance signal which is switched via a .01µF capacitor to ground to disable colour in the 1, 2 & 3 positions of switch SZb and in position 6 when S3 is closed to provide the grey scale. The composite video output at pin 6 is attenuated using a 390Q and 470Q resistive divider. The attenuated signal is buffered with transistor Q1, which is connected as an emitter follower. Its output provides a video signal to the RF modulator and to the video output socket. Both output signal paths are via 470µF electrolytic capacitors. Diodes D8 & D9 clamp the video signal to the RF modulator at ground level (necessary for correct modulation levels). The 6.8V zener diode provides the necessary supply rail for the modulator. The output of the RF modulator is at channel 2. Power for the circuit is derived from a 12VAC plugpack which drives bridge rectifier D1-D4 and a 470µF capacitor. The resulting DC rail is then fed to 3-terminal regulators REG1 & REGZ to derive the necessary +12V and +5V supply rails. Next month, we will describe the construction and testing of the pattern generator. SC