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A 2kW 24V/240VAC sinewave inverter; Pt.3 In this third article on the 2kW inverter, we present the H-pack output drive circuit which converts the 365V DC rail into 240VAC. We also describe the pulse drive circuit which enables the H-pack to produce a sinewave output. By JOHN CLARKE Last month, we described the heavy duty DC-to-DC converter circuitry which steps up 24V DC to 365V DC and we emphasised the design problems in handling currents in excess of 100 amps. But having obtained the high DC voltage, it must be converted to a 50Hz 240VAC sinewave and this presented more onerous problems 66 S1LJCON CHIP than the DC-DC conversion. Our initial approach to this part of the circuit was to use heavy duty Mosfets but this proved to be a dismal failure. These devices just could not do the job and so we turned to a hybrid device, the insulated gate bipolar transistor. These devices are available in higher current and volt- age ratings than Mosfets and enable us to design a H-pack output drive circuit which requires just four devices. This means that there is no need for paralleled devices and hence problems of uneven current sharing are eliminated. The circuit for the H-pack drive is show:n in Fig.10. This uses eight ICs (IC6-IC13), three transformers, four insulated gate bipolar transistors (IGBTs), four soft recovery diodes and associated passive components. Before we dive into the circuit description, let's just refresh our memory on the overall concept of this sinewave inverter. This is best done by referring to the block diagram ofFig.3 MOSFET DRIVERS i ANO CONTROLLER + 24V BATTERY STEP-UP TRANSFORMER x18 HIGH VOLTAGE FULLWAVE RECTIFIER HIG~ VOLTAGE LTER CAPACITOR +365V ISOLATED VOLTAGE FEEDBACK A A SWITCH 1 SWITCH 2 8 8 L2 SWITCHMODE SINEWAVE GENERATOR X C -c D SWITCH 3 D SWITCH 4 DV Fig.3: repeated from the first article, this block diagram illustrates the basic arrangement of the sinewave generator & H-pack output drive circuits for the 2kW inverter. Switches 1-4 are equivalent to the insulated gate bipolar transistors (Q17-Q20) shown in Fig.10. which we have reproduced from the first article. We won't go through the description of the block diagram again other than to point out that the H-pack circuit consists of semiconductor switches 1-4. These are fed with pulse signals from the switchmode sinewave generator which allow the circuit to produce a 50Hz sinewave, after suitable filtering. Switches 1-4 in Fig.3 are the insulated gate bipolar transistors we have already referred to. Switch 1 is Ql 7 on Fig.10, switch 2 is Q18, switch 3 is Q19 and switch 4 is QZ0. These IGBTs are Siemens BUP304 devices which have a collector-emitter voltage rating of 1000V and a continuous collector current rating of 35A. They can be pulsed at currents of up to 50A and because they have insulated gates, they can be driven in the same manner as Mosfets. Hence, each IGBT gate is driven by six paralleled 4049 CMOS inverters. So Q17 is driven by IC7, Q18 by IC9, Q19 by IC11 and QZ0 by IC13. The paralleled inverter outputs provide sufficient drive to charge and discharge the Z000pE gate capacitance which must be done to switch the IGBTs on and off. Zener diodes ZD8, ZD10, ZD12 and ZD13 protect the gates of the IGBTs against overdrive. Each 4049 hex inverter IC is driven by a fast optocoupler with an isolation rating of 5300V and a switching response time of about 0.5µs. The LED in each optocoupler is driven by the switching sinewave generator circuit yet to be described. When the LED is turned on, the transistor in the optocoupler turns on and pulls the inverter inputs low. This pulls the respective IGBT gate high and-turns it on. Conversely, when the LED is off, the IGBT is off. Isolated supply lines Turning the IGBTs on and off requires a lot more than just having a paralleled hex buffer to drive each gate, however. For the two top transistors in the H-pack (Ql 7 and Q18), each 4049 buffer requires its own isolated 15V supply. Similarly, for the other two transistors in the H-pack, the 4049s require a common but still isolated 15V supply. There are several reasons why the 15V supply used for the drive circuitry in the DC-to-DC inverter cannot be used. The first reason is that the 0V line of the 365V supply cannot be tied to the 0V line from the 24V battery. This MAINS GPO is necessary because both the . high voltage DC and the 240VAC output must be completely isolated from the battery input circuits. This is done for safety reasons and also to prevent any feedback process which might upset the circuit operation. For the top two transistors in the Hpack, there are much more compelling reasons for having the isolated supply lines for the buffers. When Ql 7 or Q18 turns on, its collectoremitter voltage drops to a very low value and so its emitter jumps to almost +365V. So when Ql 7 turns on, its emitter jumps to +365V and so does the rest of the circuitry tied to that emitter. Hence, pin 8 of IC7 and pin 5 of IC8 is also pulled to +365V. The sµme process also applies to Q18, IC9 and IC8. This means that three isolated 15V supplies are mandatory for the circuit to work. The isolated supply lines are provided by three small transformers : TZ, T3 and T4. These are driven by a common high-frequency driver circuit which operates at about 1MHz. We'll describe how this works later in the article. The secondary outputs of TZ, T3 and T4 are rectified using small signal diodes D7, D8 and D9 and the DC DECEMBER 1992 67 +365VO-------------------------------------+---------D7 1N4148 4.7k 106 SFH6136 • 1 50VW LL - 017 BUP304 8 K D10 BYP102 J A ~~~ J A G B 1W H (1) X ~ H GOE K A D9 1N4148 (3) 4.7k 1010 SFH8138 ZD11 15V 1W 1 + 50VW LL - 8 K 8 J SIOV3 S14K275 019 BUP304 1D A 5 ZD12 18V 1W K J SIOV4 S14K275 HIGH VOLTAGE SWITCHES AND FILTER is smoothed with a lOµF capacitor. The supplies are each regulated using a series resistor and a 15V zener diode (ZD7, ZD9 and ZD11 respectively), and are each bypassed with a lµF capacitor. While these three transformers are very small, the 1MHz operating frequency means that they are very efficient and quite adequate for supply68 SJLICON CHIP ing the gate current requirements of the IGBTs. IGBT voltage protection You might think that because the IGBTs have a 1000V rating, they would be rugged enough to withstand anything that the circuit could throw at them. Unfortunately, that is not true and they do require protection both for themselves and their insulating washers. Since these IGBTs do not have internal reverse diodes, as do power Mosfets, we have connected a BYP102 fast recovery diode across each one. These are D10, D11, D12 and D13. When each IGBT is switched off, its inductive load generates a very sharp voltage transient which raises the D8 1N4148 +365V 4.7k E IC8 SFH6136 ZD9 15V 1W LL - 018 BUP304 D11 BYP102 6 J ZD10 18V 1W 5 C SIOVS S14K275 1 sovw SIOVI S14K275 J D (2) 0.75mH 10A L3 0.75mH 10A L4 y FS 10A 15A Elli FILTER DELTA 10DRCG5 GPO OUTPUT 240V SOHz SINE +385V CHASSIS (4) 4.7k IC12 SFH6136 1 + S00VAC- SIOV7 S14K275 1 + 50VW LL 020 BUP304 K D13 BYP102 ). A ZD13 18V 1W II emitter above the collector in the case of Ql 7 and Q18, or pulls the collector negative with respective to the emitter in the case of Ql 9 and Q20. During switch-off, the diodes conduct and clamp the emitter of each IGBT to its collector and hence prevent reverse voltage punch-through. The BYP102 diodes are rated at lO00PIV and 50A peak, and have a SIOVI S14K275 J N response time of 130ns. Even with diode clamping, the large voltage transients produced at the instant the IGBTs switch off can cause breakdown of the insulating washers. This problem has been controlled in two ways. First, a lµF 500VAC capacitor is connected across the 365V supply rail close to the IGBTs. This effectively counteracts much of the Fig.10: the H-pack output drive circuit is based on insulated gate bipolar transistors Q17-Q20. These in turn are driven by a sinewave generator circuit (see Fig.11) via optocouplers IC6, IC8, ICtO & IC12 & hex buffer stages IC7, IC9, IC11 & 1Ct3. The optocouplers serve to isolate the highvoltage output stage from the 24V DC supply. Transformers T2-T4 & diodes D7-D9 provide isolated DC supply rails for the optocouplers & 4049 hex buffers DECEMBER 1992 69 n :r: :a z n 0 r=: C/l Q "-l I +5V 100k! 0.1 • I 2 IC14 7555 ": ": ........;t I 220pfj +5V 5 t 16 4 I ": 14 8 -·- ": 16VW 10 I 1 I I 10 3 10 ": • +5V 4 8 u n ": 14 8 CLR 5 COUNT UP 16 4 B A po~• IC15e R I ~n III 2 A3 7 2 ae E GIil A2 8 3 QA E ~,,-• I 711o.. IC15d 1 IC19 74HC193 11 A4 6 6 QC 9 AS 5 7 0D CARRY 15 10 B IGO ~ IC23 NIIC27C84N OTP-ROIi A6 4 QA AS 25 6 QC r 05 A7 3 2 QB 9 A9 24 7 QD CARRY 15 10 0.1+ I I I I I I 3 21 3 1 A11 I 23 2 ae VPP PGII A12 VCC 2 6 IC17dr. 11 0D 27 I; I .c- 2200 2200 2200 ~~~~ .... + ": 12 ": -~~~- r =\\Y, 021 ": o.1I IC17e 0.1+ ~8 15 10 QC IC21 74HC193 11 IC22d~ A10 IC22■ Y. 14 CLR QA I l I I 8 16 I I. I I I I 19 5 COUNT UP I IC17d 3 ..... - 4 ~7 08 12 ": 0.1 ! +5V:t'Q I Y. CLR 1 IC20 74HC193 11 IC22c 74HC08 10 16 4 5 COUNT UP EOc VIEWED FROM BELOW 12 ": ... o.1I LOW VOLTAGE TRANSFORMER DRIVERS AND SWITCHING SINEWAVE GENERATOR ~ 12 ": ... o.1I I I '.IC181 .... , I £""'°-c ecr-o A1 9 7 QD IC15b 1 1, AO IC15c + I 11 I CARRY 6 QC rJ 10 I 15 10 9 a IC18 74HC193 11 QA I IN~OUT REG2 Allo.. 4049 0.1+ .I. 0.1! 0.1 ! I. I COUNT UP CLR M~I • I I -: 22pf I 0.1+ 2.2ki 10 .&,. 25VW+ sw~~6~Eo 0 22pf+ ": 1011 ~- X1 3.2768MHz . • N ~ ~K t :~ supply lead inductance which causes the sudden voltage transient. Second, we have connected Metal Oxide Varistors (MOVs) across each IGBT to clamp the voltage to an acceptable level. Each IGBT has two SIOV S14K275 varistors in series, which effectively gives voltage clamping at about 780V. The H1 resistor in series with each pair of MOVs limits the breakdown current through the varistors to a safe value. Output filter The difference between the pulse ◄ Fig.11 (left): the sinewave generator circuit uses crystal oscillator stage IC17a to drive cascaded 4-bit binary counters IC18-IC21. These in turn drive the address inputs ofIC23, an OTPROM which contains the sinewave code. Its outputs, at D5 & D6, then produce pulse signals to drive the optocouplers in the H-pack output stage via transistors Q21-Q24. IC14 & its associated inverter stages provide the low voltage drive to transformers T2-T4. This close-up view shows the H-pack drive circuitry for the inverter, with the outputs from the sinewave generator circuit at bottom right. The four switching transistors (IGBTs) are bolted to the chassis on either side of the board, along with their BYP102 protection diodes. width modulated waveform at point X (ie, the junction of Q17 and Q19) and the PWM waveform at point Y (the junction of Q18 and Q20) becomes the output waveform after filtering. This filtering is provided by inductors L3 and L4 and the 25µF 3 70VAC capacitor connected between points X and Y. While the switching rate of the IGBTs is 4kHz, the filter cutoff frequency is set to about 820Hz to produce a smooth sinewave as depicted in the photographs published last month. However, this filtering is not sufficient to avoid interference to radio and TV reception. Hence, further filtering is provided by a commercial EMI filter rated for load currents of up to 10 amps. Sinewave generator That concludes the description of H-pack circuit ofFig.10. We now need to refer to the diagram ofFig.11 which shows the sinewave generator and high frequency transformer drivers. The latter provide the isolated 15V supplies via transformers T2, T3 and T4 . The transformer driver circuitry comprises IC14, IC15 and IC16. IC14 is a CMOS 555 timer which is connected to produce a square wave with a duty cycle of 50%. Unlike the usual 555 circuit configuration, the output at pin 3 charges and discharges the 220pF capacitor at pin 2 and pin 6 via a 2.2kQ resistor. At switch-on, pin 3 is high and the 220pF capacitor charges via the 2.2kQ resistor until the voltage across it reaches 66% of the 15V supply. Pin 3 then switches low and discharges the 220pF capacitor via the 2.2kQ resistor until thEp voltage reaches 33% of the 15V supply. This causes pin 3 to again go high and so the cycle repeats. The frequency of the square wave at pin 3 is about 1MHz. The output of IC14 is buffered by IC15a, a 4049 inverter. This in turn drives inverters IC15b, IC15c and IC16a. IC15b and IC15c are connected DECEMBER 1992 71 The sinewave generator board carries the low-voltage transformer drive circuitry & the NMC27C64N OTPROM. This board is mounted on the bottom of the case & its outputs connected to the H-pack output board via flying leads. in parallel to drive IC15d, IC15e and IC15f. IC16a drives paralleled inverters IC16b and IC16c which in turn drive IC16d, IC16e and IC16f. The buffered outputs from these stages then drive the primary windings of transformers T2, T3 and T4 on the H-pack output PC board. . The circuitry for the sinewave generator includes four 4-bit synchronous counters (IC18-IC21), an BK x 8 OTPROM (see below), a 4049 hex inverter (IC17), a quad 2-input AND gate (IC22) and four transistors (Q21-Q24). CMOS inverter IC17a is connected as a crystal oscillator operating at 3.2768MHz. Its output signal appears at pin 8 and is applied to the clock input (pin 5) of binary counter IC18. The four binary counters (IC18IC21) are cascaded together to divide the 3.2768MHz signal. These counters are synchronous types which means that their outputs at QA, QB, QC and QD all change together with the clock input. IC23 is an BK x 8 One Time Programmable Read Only Memory (OTPROM). The only practical difference between an OTPROM and an EPROM is that an OTPROM can only be programmed once while an EPROM 72 SILICON CHIP can usually be programmed and erased many times. Since the OTPROM does not have a window in the package, it is quite a bit cheaper. IC23 contains the code for one half of a complete sinewave. It has 13 address lines and these are driven by the Q outputs of the binary counters. Two of its data lines, D5 and D6 at pins 16 and 17, then produce the necessary pulse signals to drive the Hpack output stages. Since the frequency fed to the AO input is 409.6kHz (3.2768MHz divided by 8), the frequency fed to the A12 input is 100Hz (409.6kHz divided by 4096) and this provides exactly half the period for a 50Hz sinewave. Because IC23 counts up from 0 when all its address inputs are low (0) to 8192 when all its address inputs are high (1), the OTPROM produces a high and low signal sequence at its D5 and D6 outputs. IC17b inverts the QA output ofIC18 and drives the G-bar input to IC23, pin 22. When the G-bar input is low, the data outputs (D5 and D6) of IC23 have a low impedance. Conversely, when the G-bar input is high, the data outputs are in a high impedance state. When the address lines of IC23 change to the next count, there is a short time when the data outputs are invalid since the OTPROM has a finite access time of 250ns. To cope with this problem, the G-bar input is held high (QA ofIC18 is low) and the data outputs are in a high impedance state for 305ns between each valid code. It may appear to be bad design to have the data outputs at D5 and D6 in a high impedance state for this brief time interval. After all, these outputs are driving the CMOS inputs of quad AND gate IC22. In practice though, it is not a problem since the input capacitance of the AND gates acts to maintain the last valid code. When the data outputs return to their low impedance state, they drive the CMOS inputs in the normal way. AND gates IC22a and IC22d each have one input connected to the QD output of counter IC21. This output is also inverted by IC17e to drive one input of AND gates IC22c and IC22b. Since QD is a 50Hz square wave, it is high for 10ms and low for 10ms. Thus, QD effectively controls the AND gate package and determines which of the four driver transistors (Q21-Q24) receive the switching signal from the OTPROM. IC22a drives transistor Q23 which drives optocoupler IC10 and transistor Q19 on the H-pack board. Similarly, IC22b drives transistor Q24 and this in turn drives optocoupler IC12 and Q20. The D6 output of IC23 therefore controls the lower switches of the Hpack. Similarly, the D5 output ofIC23 controls the upper switches of the Hpack. These separate outputs allow dead time to be included in the sinewave generation coding between opposing switches. For example there is dead time between the '1' switch turning off and the '3' switch turning on. Power supply Power for the circuit is derived via REG2 which regulates the 24V supply to provide a +5V rail. The series 150Q resistor limits the current through ZD14 which is included to protect the input of the regulator. The 10µF capacitors at the input and output of REG2 provide supply decoupling. That concludes the circuit description of the 24V/240VAC sinewave inverter. Next month, we will describe the construction of the DC-to-DC converter board. SC