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AMATEUR RADIO BY GARRY CRATT, VK2YBX A PLL demodul-ator for FM • amateur receivers The use of a phase locked loop to demodulate FM signals is largely overlooked in conventional receiver designs, which normally use quadrature detectors.·By comparison, a PLL FM detector can be simpler, cheaper and easier to align. To understand why a PLL is such a good FM detector, it is necessary to first know how such a circuit operates. The basic PLL concept has been known and widely used since 1922. Since that time, PLLs have been used in instrumentation, -space telemetry, and many other applications requiring a high degree of noise immunity and narrow bandwidth. PLL block diagram A block diagram of a PLL is shown in Fig.1. Phase locked loops operate by matching their internal oscillator frequency to that of an input signal, Fin• In the "locked" condition, any variation in the input frequency appears as a phase change between Fin and the internal oscillator frequency. This phase shift acts as an error signal which causes a change in the internal oscillator frequency to "track" the input frequency. The action of locking onto the phase difference between Fin PHASE COMPARATOR and the local oscillator frequency is the basis of the name, "phase locked loop". Conventional circuitry for the reception of FM signals involves the use of a quadrature detector, such as the ever popular MC3357 and its derivatives. But although such circuits provide good performance, they invariably require the use of an external oscillator or, at the very least, a crystal to mix to a (lower) frequency before detection takes place. In addition, the bandwidth of such a circuit must be set by an external filter, incurring additional costs and complexity. In short, such circuits may be suited to mass production but they cannot easily be duplicated on the kitchen table. PLL advantages A PLL circuit has significant advantages over the quadrature detector as far as complexity is concerned. The LOW-PASS FILTER VOLTAGE CONTROLLED OSCILLATOR Fig.1: this is the block diagram for a phase lock loop (PLL). The phase comparator produces the error signal to control the oscillator. This configuration is widely used in both digital and analog circuits. 66 SILICON CHIP frequency range over which the PLL operates is controlled by a single DC voltage which sets the centre frequency. No external filter is required to produce an operational circuit. The NE564 PLL featured in this article can be configured to "detect" at input frequencies of up to 50MHz without external mixers. Hence, it is ideally suited for operation at the intermediate frequencies (IF) used in typical VHF or UHF transceivers; ie, 10.7MHz, 21.4MHz and 45MHz. Practical PLL detector In fact, a complete IF strip can be built using less than 20 passive components, with frequency adjustment controlled by a single trimmer capacitor. Fig.2 shows our circuit for a 10. 7MHz PLL detector. The input signal is fed to pin 6 of the NE564 and the audio output is produced at pin 14. Loop filtering is provided by the network attached to pins 4 and 5, while the oscillator frequency is set by the capacitance between pins 12 and 13. Apart from DC connections to pins 1, 3, 9 & 10, the only other control required is the "bandwidth" control, and this is provided by the lOkQ trimpot (VRl) feeding pin 2 of the PLL. As with all FM communications systems, use is.made of pre-emphasis and the RC network at pin 14 performs the appropriate de-emphasis. The entire circuit is designed to operate from 5V, although it can be run from 12V by changing the value of the lkQ resistor feeding pins 3 and 9 to 4700 and adding a 220n resistor in the DC feed to pin 10. The layout of the circuit is not critical at 10. 7MHz, although more care ...---------~+SV VR1 10k 1k ~--- 3 9 1 10 RF INPUT .0022 14 IC1 NE584 1k AUDIO OUTPUT 39k .0022+ .022! 8 4 22011 22011 .0022+ .0022+ ":' Fig.2: this circuit is intended to act as a demodulator following a 10.7MHz IF stage in an FM receiver. It requires virtually no alignment and is easy to build . Silicon Chip Binders 13 12 39pf VC1 0-20pf should be taken if you wish to operate the circuit at 50MHz, particularly regarding the length of component leads. At this frequency, it's important that component leads be kept short. Alignment Alignment is easy and requires only a frequency counter. The local oscillator frequency (and hence the detection frequency) can be measured at either pin 12 or 13, both of which are connected to the internal VCO circuit. Hence, to set up the PLL for operation at 10.7MHz, you simply adjust trimmer capacitor VC1 while measuring the frequency. To calculate the frequency of the VCO for a given capacitance, the following formula should be used: f0 = 1/[22Rc(C1 + Cs)l where Re is an internal 100n resistor, C1 is the external frequency setting capacitor, and Cs is stray capacitance. Comprehensive applications notes and data on the NE564 are provided in the Signetics Linear Manual, Volume 1: Communications, 1987. SC These beautifully-made binders will protect your copies of SILICON CHIP. They are made from a distinctive 2-tone green vinyl & will look great on your bookshelf. Price: $A 11 .95 plus $3 p&p each (NZ $6 p&p). Send your order to: Silicon Chip Publications PO Box 139 · Collaroy Beach 2097 Or fax (02) 979 6503; or ring (02) 979 5644 & quote your credit card number. 1 IAN J. TRUSCOTT S ELECTRONIC WORLD 30 Lacey Street, Croydon 3136 . Phone: (03) 723 3344. Fax: (03) 725 9443. Now also at: 200 Smith Street, Collingwood. Phone: (03) 419 2808. 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