Fullscreen HTML5Med Res (??MB)HTML4

Windows-based digital logic analyser This PC-based digital logic analyser uses software dev­eloped for Windows 3.0 or higher. It features eight input channels & can be built for less than $220.00. By JUSSI JUMPPANEN There are basically three choices when it comes to debug­ging digital electronic circuitry. In order of preference, these are: (1) a commercial digital logic analyser (expensive); (2) an oscilloscope; and (3) a logic probe or digital multimeter. Of these, the latter method is the most common, although it is the least effective. Although far superior to a DMM or logic probe, a CRO suff­ers from several major drawbacks. First, it is specifically designed for testing analog 36  Silicon Chip circuits. Analog signals are more than likely to be of a periodic nature and a CRO requires a periodic signal for triggering. Unfortunately, many digital signals are non periodic and so cannot be displayed effectively on a CRO. For example, the read cycle of a RAM circuit or the one-shot action of a pushbutton circuit are difficult to debug using a CRO. In addition, the average CRO only has two channels. When analysing digital circuitry, the more channels that can be exam­ined simultaneously the better. After spending many a frustrating hour trying to debug digital electronic circuits using a 2-channel CRO, I decided that there had to be a better way. Unfortunately, commercial logic analysers are expensive and so this project was developed as a low-cost alternative. In particular, costs have been kept low by making the system PC-based. This provides a very effective display for the logic analyser. The control software is based on the Windows 3.0 platform and this not only simplifies the software development, but also results in an easy-to-use, professional-looking package – see Fig.1. The result is a 6.0MHz bandwidth, 8-channel digital logic analyser for less than $220.00. It boasts a host of features, including programmable trigger, variable sample fre­quency and external clock support. The programmable trigger allows the circuit to trigger on four of the eight input channels, while the frequency control allows the sampling frequency to be to be varied linearly from 100kHz to a maximum of 6.0MHz in 100kHz steps. If required, a lower sampling frequency can be provided by connecting an exter­nal clock to the unit. Software features The software is the heart of the project and was written using the Borland 3.0 C++ compiler in conjunction with the Bor­land Object Windows Library for Windows 3.0. It was initially tested on a machine running OS/2 2.0 using OS/2’s WinOS2 support but also runs on machines running Windows 3.0 and Windows 3.1. The software carries out three broad functions: (1) hard­ware configuration and control; (2) data storage and retrieval; and (3) data analysis and display. The hardware control is provided through the use of I/O read and write ports. The software allows the user to program the trigger point at which the logic analyser starts sampling and program the frequency at which the sample should run. Normally, once started, the sample is taken within a few milliseconds. If the circuit does not trigger, the sample will run indefinitely. For this reason, an ABORT button is also provided to enable the current sample to be cancelled. Once a sample has been completed, the software automatical­ ly displays the results of the sample on the screen. Several tools are provided by the software to help analyse the resulting data. First, the display timebase can be modified to any one of four settings (x1, x2, x4 or x8). The sample data is made up of 1024 individual samples and so it is not possible to display all the results on the screen at the same time. The timebase feature allows the user to select the amount of data that is to be displayed. For example, a x8 timebase will display eight times as much data on the screen as a x1 timebase. But even with the multiple timebase feature, not all the data can be displayed at once. To cater for this, the software allows the user to scroll Fig.1: the opening screen displays the demonstration sample when the software is first booted up. You can vary the sampling frequency from 100kHz to 6.0MHz in 100kHz steps by clicking on the Up & Down arrows & choose from one of four timebase settings. Fig.2: clicking on Edit Trigger brings up the Trigger Selection dialog box. Triggering is controlled by the first four channels & these can be set to trigger on a high, low or don’t care state. This command can also be activated by double-clicking the left mouse button in the data display area. the display, thus allowing different sections of the sample data to be examined. A status bar shows the currently displayed sample number and also shows the hex value of the sample. To help locate a particular sample value, the software also provides a comprehensive search feature. It is possible to search for a specific value on any one of the eight channels or for combinations of values on any or all channels. It is also possible to measure the period and frequency of any two points shown on the display area. The actual frequency and period, as calculated by the software, are based on the sam­pling frequency. This results in June 1993  37 VCC 16 1 15 R1 1k R2 1k R3 1k R4 1k R5 1k R6 1k R7 1k GND GND GND BD7 BD6 BD5 BD4 BD3 BD2 BD1 BD0 IOR IOS IOU ALE BA7 BA6 BA5 BA4 BA3 BA2 BA1 BA0 TRO3 TRO4 CLOCK IO RDY AEN 2 2 S5 4 14 3 S3 6 13 4 S1 8 12 5 S0 11 11 6 S2 13 10 7 S4 15 9 8 S6 17 +12V VCC -12V -5V 3 A15 5 A13 7 A11 1 9 A9 20 12 A8 2 14 A10 21 16 A12 3 18 A14 22 1 AEN 4 14 2 P0 P=D P1 U2a 19 1 U3e 74LS04 11 14 10 IOR 3 P2 12 13 U2d P3 IOS 11 P4 5 P5 P6 74LS02 U2b 6 P7 U1 D0 74LS688 4 13 U3f 12 7 7 IOU IOU D1 D2 D3 D4 D5 D6 D7 G 23 10 5 ADDRESS DECODING 24 6 25 7 VCC VCC 26 20 8 27 D7 9 D6 28 D5 10 D4 29 D3 11 D2 30 D1 12 D0 31 IOS 13 IOR 32 14 2 3 4 5 6 7 8 9 19 1 20 A0 B0 A1 B1 A2 B2 A3 B3 A4 A5 U4 74LS245 B4 B5 A6 B6 A7 B7 18 17 16 15 14 13 12 11 BD7 2 A7 BD6 A5 BD5 A3 BD4 A1 BD3 A0 BD2 A2 BD1 A4 BD0 A6 E 4 6 8 1A1 1Y1 1A2 1Y2 1A3 1Y3 1Y4 U5 11 74LS244 2A1 2Y1 13 2Y2 2A2 15 2Y3 2A3 17 2Y4 2A4 1G 2G 1A4 1 DIR 18 16 14 12 9 7 6 3 BA7 BA5 BA3 BA1 BA0 BA2 BA4 BA6 19 10 10 BUS BUFFERING 33 15 34 16 35 RESET 20 S7 S1 SW-DIP8 GND IOR R8 1k 17 VCC C1 0.1 C2 0.1 36 C3 0.1 C4 0.1 C5 0.1 DECOUPLING 18 37 19 J2 DB37/F I/O PORT CONNECTIONS I/O BUS EXPANDER Fig.3: the circuit details for the internal I/O card. The location of the logic analyser in the I/O map is set by S1, with U1 performing partial address decoding on address lines A15-A8. Bus transceiver U4 provides data bus isolation for the D0-D7 data lines, while U5 buffers the A7-A0 lines. a very accurate measurement of both frequency and period. The display can also be configured 38  Silicon Chip in a number of different ways. First, it is possible to change the labels associated with any or all of the channel traces. Second, it is possible to temporarily hide any unwanted traces on the display. And third, the colour of the display can be configured to suit personal taste. Once a sample has been taken it is possible to save the results to file. A descriptive note can also be added to the saved results. The data can then easily be read back at a later date for further analysis or even further testing. Hardware – internal card The software controls two pieces of hardware: (1) an inter­nal XT bus card (or I/O Port Card); and (2) an external logic analyser board. The internal card will work in either an XT or AT bus slot. Its sole purpose is to provide a means of addressing the external logic analyser board. It provides basic I/O decoding and maps the I/O addressing signals to a 37-way D-type connector. Fig.3 shows the circuit details of the I/O Bus Card. Address decoding The internal card will work in either an XT or an AT bus slot. It provides basic I/) decoding & maps the addressing signals to a 37-way D-type connector. A point to note here is that because I/O address signals are only partially decoded (ie, A18-A15), the internal card reserves a full 256 consecutive I/O address lines. This may seem wasteful but the circuit was specifically designed this way to allow external boards to be cascaded (more on that later). To guarantee that the circuit works correctly, the I/O address must be configured so that it doesn’t clash with any existing I/O devices. This means the card must be addressed to a portion of the I/O map that contains 256 consecutive unused I/O address locations. The 8086 architecture provides over 65,000 I/O address locations from which to choose and, on most machines, I/O devices are located at the lower end of the I/O address space. So to ensure that the card functions correctly, it is best to use a high address space (an address that seems to work well is 0F30H). External logic analyser board The external logic analyser board performs all the actual processing required to sample eight digital input channels. The board can be divided into the following regions: address decod­ing, hardware control registers, clock generation, trigger pro­gramming and the RAM storage unit. Fig.4, Fig.5 & Fig.6 show the details. The external logic analyser board takes all its control signals from the DB37/M expansion port. It decodes the remaining A7-A0 I/O address lines using U100, a 4-bit comparator, and S100 (the 4-bit DIP switch) – see Fig.4. The result of the comparison is used to partially enable U101 and U102, the two 3-line-to-8-line decod­ers. By using the IOR-bar and IOU-bar signals to further enable U101 and U102 respectively, we end up with eight active low I/O write signals and eight active low I/O read signals. The logic analyser requires the use of 3 I/O write and 2 I/O read address lines which are configured as shown in Table 1. The output DB37/F expansion port is used to connect to a possible second external board. The two octal bus transceivers, U103 and U104, are used to provided additional line drive for the outgoing expansion port, while U103 also provides data bus isola­tion. The philosophy behind this is to allow external boards to be cascaded. ▲ The location of the logic analyser in the PC I/O map is controlled by a DIP switch (S1). The 8-bit DIP switch setting is compared with the A8-A15 high order address lines of the XT address bus using U1, an 8-bit comparator. The remaining lower order address lines (A7-A0) are passed to the external board through the D37 expansion port. This means that the internal card only partially decodes the address lines and relys on the external board to complete the full decoding process. The result of the address comparison is combined with the XT bus IOR and IOU signals by NOR gate U2 and hex inverter U3 to produce three active low I/O signals: IOS-bar, IOU-bar and IOR-bar. The IOS-bar signal is active low when the I/O address match­es the S1 DIP switch setting, thus indicating a valid I/O ad­dress. The IOR-bar and IOU-bar lines indicate that a valid I/O address is being sent to the D37 expansion port. These correspond to read and write cycles, respectively. The IOR-bar and IOS-bar lines also feed into U4, the bus transceiver, to provide proper data bus isolation whenever the board is not selected. U4 also provides additional data bus line drive and helps protect the PC data bus. The low order address lines (A7-A0) feed out through the D37 expansion port via U5, an octal buffer. This chip is there to provide extra address line drive and to protect the PC address bus. Fig.4: the external logic analyser circuit takes all its control signals from the DB37/M expansion port & decodes the remaining A7-A0 address lines. The result is then used with the IOR-bar & IOU-bar signals to enable U101 & U102 to derive the I/O write & read signals. IC13, IC20 & IC21 synthesise the sample clock signal. June 1993  39 40  Silicon Chip June 1993  41 VCC CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 IC1a 14 1 13 20 2 BCH7 IC1f 74LS14 12 BCH7 1 LA 11 LCLK BCH0 3 3 11 5 IC1b IC1e IC1c 4 BCH7 BCH1 18 BCH2 17 BCH3 10 BCH3 BCH4 BCH5 6 BCH4 BCH6 BCH7 9 13 1 IC1d IC2e OE OD0 D0 D0 CLK OD1 D1 D1 OD3 D2 D2 OD2 D3 D3 D0 D0 D1 D1 D2 D2 IC3 4 D3 74LS374 14 D4 7 D5 13 D6 8 D7 8 BCH5 12 BCH6 3 20 D3 D4 D5 D6 D7 2 19 16 5 15 6 12 9 CD0 CD1 CD2 CD3 CD4 CD5 CD6 OD5 IC4 D4 74LS374 D4 OD4 D5 D5 OD7 D6 D6 OD6 D7 D7 IOU2 CLK OE CD7 1 2 TA0 TA0 10 19 TA1 TA1 12 16 TA3 TA2 13 5 TA2 TA3 15 15 M1 6 TB0 9 M0 12 M3 9 M2 VCC M0 10 10 BCH0 BCH1 CHANNEL BUFFER BCH2 IC2a 74LS14 1 BCH7 BCH3 7 74LS08 1 14 IC5a M1 2 5 M2 4 9 M3 10 12 IC5b IC5c IC5d 13 3 TB0 6 TB1 8 TB2 TB1 11 TB2 14 TB3 1 A0 16 A=B A1 A2 A3 IC6 74LS85 B0 6 TRIG B1 B2 B3 A<B A>B 2 4 8 11 TB3 7 TRIGGER CIRCUIT Fig.5: the input data is buffered by Schmitt trigger stages IC1 & IC2 & clocked into IC3, an 8-bit latch. Once latched, the data byte is then written into RAM (IC10) by the write cycle. IC4, IC5 & IC6 form the trigger circuit. This means that multiple external boards can share a single internal card, provided they are mapped to a unique I/O address space. Hardware control registers The software can monitor the status of the hardware by reading the status byte located at IOR0. The status byte is defined as shown in Table 2. The DONE signal indicates when the sample is complete. The software monitors the DONE line to decide when to end the sample cycle and start the read cycle. The INT/EXT signal indicates if the board is currently using its internal or external sample clock, while the TRIG signal indicates if the trigger circuit is currently triggered. The software controls the logic analyser using two 8-bit latches (IC17 & 1C16). The software writes control information to either of these latches by addressing IOU0 or IOU1 respectively. The definition of the two control bytes is as shown in Table 3. The clock data allows the software to program the sample clock generation circuit. The 7-bit clock data makes up the clock divider count, as used by the phase lock loop (IC13) to synthesise the sample clock signal. The LA-bar bit (pin 2, IC16) controls access to the logic analyser data bus. Because the PC and the logic analyser both need to access the RAM, there exists a possibility of bus contention. To protect against this, the LA-bar signal mutually excludes the PC and the logic analyser from accessing the data bus. When LA-bar is low, the logic analyser has control of the bus, TABLE 2 Bit No. Name Description 0 DONE Active high indicating sample complete 1 TRIG Active high indicating circuit triggered 2 INT/EXT Clock source: 0 = internal clock, 1 = external clock 3-7 Not Used Spare TABLE 3 IOW0 Control Byte: TABLE 1 Bit No. Name 0-6 Clock Data Clock divider data byte 7 Not Used Spare I/O Line I/O Read I/O Write 0 Status Register Frequency Divider 1 RAM Data Control Register 2 Spare Trigger Control Bit No. 3 Spare Spare 0 LA 4 Spare Spare 1 RSET 5 Spare Spare 2-5 Not Used 6 Spare Spare 6 START 7 Spare Spare 7 ALWAYS 42  Silicon Chip Description IOW1 Control Byte: Name Description Bus control signal: 0 = logic analyser, 1 = PC Software controlled hardware reset signal Spare Enable sampling circuit Not currently used Conversely, when LA-bar is high, the PC has control of the bus. The RSET signal enables a software controlled hardware reset, while the the START signal is used to control the hardware sampling. To enable the hardware, the START signal must be high. The ALWAYS signal is not currently used. Clock generation The clock signal is produced by hex inverters IC15f & IC15e. The resulting 2MHz output is divided by 10 in IC19 to produce a 200kHz clock signal. This is then further divided by 2 in D-type flipflop IC12A to produce a 100kHz base clock. The base clock is used by the phase lock loop (IC13) to synthesise a programmable sample clock signal. The PLL takes the base clock as the input frequency and compares it to the feedback clock, produced by a clock divider circuit. This divid­ er circuit consists of IC20 and IC21, which are 4-bit up/down coun­ ters. The PLL works by locking the feedback clock signal (IC13, pin 3) to the input clock signal (IC13, pin 14). Once locked, both clocks run at the same frequency – in this case, the fre­ quency of the input clock. Thus, we can write the following equa­tion: Input clock frequency = feedback clock frequency. The feedback clock is derived from the sample clock (IC13, pin 4) by dividing the sample clock by a programmable value of N. Thus, we can also write: Feedback clock frequency = (sample clock frequency)/N, where N is the divisor programmed into the clock divider circuit via the control registers. By now combining the above two equations , we get the following equation: Input clock frequency = (sample clock frequency)/N. Finally, because the input clock is fixed at 100kHz, we can re-arrange this equation to obtain the following result: Sample clock = N x 100kHz The software allows a value of N = 1 to N = 60 to be pro­grammed into the clock divider circuit. This means it is possible to select a sample clock frequency anywhere in the range from 100kHz to 6MHz in 100kHz steps. As a final option, switch S1 provides selection between the internal clock and an external clock signal. However, the logic analyser circuit can only be guaranteed to work up to 1 1 the maximum sample clock rate GND GND 20 20 of 6.0MHz and so the external GND GND 2 2 clock should also be limited to GND GND 21 21 this value. GND GND 3 3 The external clock feature BD7 OD7 22 22 is basically provided for cases BD6 OD6 4 4 where a very slow clock speed BD5 OD5 23 23 BD4 OD4 is required. The external clock 5 5 BD3 OD3 must be a TTL signal and thus 24 24 BD2 OD2 must conform to TTL specifica6 6 BD1 OD1 tions in terms of maximum and 25 25 BD0 OD0 minimum voltage levels and rise 7 7 IOR IOR and fall times. 26 26 IOS IOS The selected clock signal 8 8 IOU IOU is fed through a clock timing 27 27 ALE ALE circuit made up of IC14, IC24 9 9 BA7 OA7 & IC2. These ICs generate cor28 28 BA6 OA6 rect clock timing and phase as 10 10 BA5 OA5 required by the RAM to ensure 29 29 BA4 OA4 that the data write cycle works 11 11 BA3 OA3 correctly. 30 30 BA2 OA2 A point of interest is the role 12 12 BA1 OA1 of IC18 (the tri-state gate) and 31 31 BA0 OA0 IC24d (the 2-input AND gate). 13 13 TRO3 TRO3 Because both the software and 32 32 TRO4 TRO4 the hardware access the RAM, 14 14 CLOCK CLOCK there is some possibility of 33 33 bus conflict. IC18 ensures that 15 15 IO RDY IO RDY the sample clock (and thus the 34 34 ADDE ADDE sample write cycle) is disabled 16 16 when the software is reading 35 35 the RAM. 17 17 RESET RESET IC24d provides a method for 36 36 +12V +12V reading the RAM via software. 18 18 VCC VCC When the software reads the 37 37 -12V -12V RAM, it uses the IOR1 line. By 19 19 -5V -5V feed­ing this signal into IC24d, a rising edge ACLK signal is genOUTPUT INPUT DB37/F DB37/M erated at the end of every IOR1 I/O CONNECTORS read. This rising edge causes the RAM address counter circuit Fig.6: the pin assignments for the DB37 (IC7, IC8 & IC9) to increment, input & output connectors on the external card. meaning that the RAM counter then addresses the next RAM location. it to the 4-bit OR mask to produce the Thus, the software can read all 1024 TRIG (trigger) signal. RAM locations by just using the RSET When the TRIG level goes high, this line to initially reset the RAM address indicates that the trigger criteria has counter circuit and by reading the been met and so a rising edge trigger IOR1 address line 1024 times. pulse is generated. This method of triggering means Trigger programming circuit that the trigger circuit can be proThe trigger circuit is made up of grammed to operate on any combinaIC4, IC5 & IC6 – see Fig.5. The soft­ tion of the first four input channels. ware latches the trigger data into For example, to get the circuit to IC4, an 8-bit octal latch, using the trigger on a high level for channel #1 IOU2 address line. The trigger data and on low levels for the remaining is made up of a 4-bit AND mask and three channels, the software would a 4-bit OR mask. IC5, a quad 2-input write out the following data to the trigger circuit: AND gate, gates the first four input channels and the 4-bit AND mask. Trigger Byte AND Mask OR Mask The 4-bit result is then fed into IC6, 11111000 (F8H) 1 1 1 1 1000 a 4-bit comparator, which compares It is also possible to program the June 1993  43 PARTS LIST 1 PC board for internal card 1 PC board for external card 1 DIP switch (DIP8) 1 DIP switch (DIP4) 1 DPDT toggle switch 1 RCA panel socket 1 2MHz crystal (XTAL) 1 plastic instrument case, 260 x 80 x 190mm 1 0.6-metre length of 40-way IDC ribbon cable 9 mini IC clips (8 red, 1 black) 1 software package D Type Connectors 1 DB37/F - long footprint, PCB mount (J2) 1 DB37/F - short footprint, PCB mount 1 DB37/M - short footprint, PCB mount 1 DB37/F IDC connector 1 DB37/M IDC connector 1 DB15/F IDC connector 1 DB15/M solder bucket with case Sockets 2 14-pin DIL 1 16-pin DIL 1 20-pin DIL 1 24-pin DIL 1 16-pin IDC Semiconductors 1 74LS688 (U1) 1 74LS02 (U2) 2 74LS04 (U3, IC15) 4 74LS245 (U4, U103-104, IC11) 1 74LS244 (U5) 2 74LS14 (IC1, IC2) 4 74LS374 (IC3, IC4, IC16, IC17) 3 74LS08 (IC5, IC23, IC24) 2 74LS85 (IC6, U100) 6 74LS193 (IC7, IC8, IC9, IC19, IC20, IC21) 1 6116 (IC10) 1 74LS74 (IC12) 1 74HCT4046 (IC13 – Philips) 1 74LS32 (IC14) 1 74LS125 (IC18) 1 74HCT4040 (IC22) 2 74LS138 (U101, U102) Capacitors 1 0.47µF 37 0.1µF monolithic 1 2200pF Resistors (0.25W, 5%) 2 10kΩ 1 100Ω 12 1kΩ 44  Silicon Chip trigger with a “don’t care” option. For example, if we want the circuit to trigger only when channel Ω1 goes high, the trigger would be programmed as follows: Trigger Byte AND Mask OR Mask 10001000 (88H) 1 0 0 0 1000 In this case, the AND mask will only allow channel #1 data to pass. The comparator will always match the three don’t care channels as they are always 0. Thus, the trigger signal will only go high when channel #1 goes high. Control of the trigger circuit is achieved via the software interface. This provides an easy-to-use dialog box interface to allow selection of any trigger combinations. The resulting TRIG signal is fed into IC12b, a D-type flip­flop. This signal clocks the START data to the flipflop output to give the TRIP signal. This must be high for the circuit to start sampling. Thus, sampling will only every occur if the circuit is triggered and the software has set the START signal high. This allows the software to control the sampling by controlling the level of the START signal. Once the trigger has been latched, the sampling cycle be­ gins. Ripple counter IC22 keeps track of the number of samples taken. Once 1024 samples have been taken, the DONE signal goes high. This signal is fed back to hex inverter IC2, which disables any further sampling. The software monitors the state of the sample by reading in the DONE signal via the status register and when this signal goes high, the software ends the sample cycle and initiates a read cycle. Ram storage circuit The input data is buffered by Schmitt trigger inverters IC1 and IC2 – see Fig.5. The input buffer not only squares up the input signal but also protects the remainder of the circuit from over-voltage. By buffering the input and installing these two ICs in sockets, any damage due to over-voltage can be repaired simply be replac­ ing the ICs. Note: this circuit is only designed for TTL voltage levels so care must be taken when sampling data, to ensure that excess voltages are not applied. IC3, the 8-bit latch, takes the buffered input channel data. This data is clocked in at the rate of the sample clock (LCLK). Once latched, the data byte is written into RAM by the write cycle. The latch is also used to protect the data bus from bus contention. If the bus is in use by the PC (ie, LA-bar is high), the latch drives its outputs to a high impedance state, thus allowing the PC to have uninterrupted access. The RAM address counter is made up using IC7, IC8 & IC9 which are cascaded to form a 12-bit UP-counter. This counter is driven by the sample clock signal ACLK. The least significant 10 bits of the 12-bit count make up the sample address and are fed into IC10, a 6116 RAM chip. Note that the counter reset pin is tied to the software controlled RSET line signal, thus allowing the counter to be reset by software. IC11, an octal bus transceiver, gives the PC access to the logic analyser data bus. The PC software uses the IOR1 read signal to enable IC11, which in turn allows the PC to read the RAM data bus. That’s all we have space for this month. Next month, we shall resume with the construction and installation details. As well, we’ll describe how the SC Digital Logic Analyser is used. Where to buy the kit The kit is offered in three formats: (1). A complete kit consisting of all the parts as listed – price $215.00 plus $10.00 for postage and handling. (2). A complete kit of all parts except for the instrument case – price $185.00 plus $5.00 for postage and handling. (3). Two double-sided PC boards (with screened overlays) plus software – price $90.00 plus $5.00 postage and handling. To order, send cheque or money order to Jussi Jumppanen, PO Box 697, Lane Cove 2066, NSW. Phone (02) 428 3927. Please specify whether a 5¼-inch or 3½-inch disc is required. Note: copyright of the two PC boards for this project is retained by the author.