Fullscreen HTML5Med Res (??MB)HTML4

Lesson 2 Programming the Motorola 68HC705C8 microcontroller In Lesson 1, we discussed the following: (1) Programming Concepts; (2) Machine Code; (3) Mnemonics; (4) 6805 Programming Model; (5) Flowcharts. In this lesson, we will discuss Addressing Modes. To write a program for a micro­ controller, we need to go from a concept to machine code. The concept may be made easier to follow by using a flow chart, from which we can start writing mnemonics. The mnemonics and an addressing mode will enable us to arrive at the machine code which will ultimately run in our micro­ controller. Mnemonics The MC68HC705C8 has instructions that are one, two or three bytes long, depending on what they have to do. We refer to the differences in length of these instructions as addressing modes. The MC68HC705C8 has 62 basic instructions and 10 different ad­ dressing modes, giving a total of 210 different op-codes. Table 1 shows the 6805 CMOS mnemonics and addressing modes. It is usually referred to as the instruction set. If you count the mnemonics in the instruction set, you will get more than 62. This is because some of the mnemonics are repeated and some have the same op-code. When you write a program for a microprocessor, some mnemon­ i cs are straightforward and require need no further information; eg, Transfer Accumulator to indeX register (TAX), or CLear Carry bit (CLC). However, some instructions, like LoaD Accumulator (LDA) or STore Accumulator (STA), do need more information; eg, load with what or load/store from/to 80  Silicon Chip where? The added information, if any, and the length of the instruction (in bytes) is governed by the addressing mode. In this lesson, we will explain three of these addressing modes: (1) Inherent Addressing Mode Symbol for Inherent addressing: none. The CPU only requires one byte of data to process this in­struction. This byte is the opcode. All information required by the CPU is “inherently” known. In other words, the instruction needs no further information from the programmer. The first three addressing mode columns in Table 1 are inherent (INH), inherent accumulator (INHA) and inherent index register (INHX). The latter two are sometimes referred to as register addressing modes but in these lessons we will class them as inherent; eg, DECA, DECX, NOP, SWI, COMA, STOP, RORA and ROLX. (2) Immediate Addressing Mode Symbol for Immediate addressing: # The CPU requires two bytes of data to process this instruc­tion. The first byte is the op-code, while the second byte is the operand. The CPU requires the operand (byte) immediately follow­ing the op-code. This byte is known at the time the program is written and it becomes a permanent part of the program. The programmer uses the immediate byte for things like setting outputs, maths, logic and compare variables, etc; eg, ADD #, AND #, ORA #, EOR #, LDA #, LDX #, CMP # and CPX # (3) Extended Addressing Mode Symbol for Extended addressing: $$ or none. The CPU requires three bytes of data to process this in­struction. The first byte is the op-code, while the second and third bytes are the High and Low address (16-bit word) of the operand in memory. The CPU requires the operand (byte) which is extended any­where in mem­ ory. The memory location for this byte is known at the time the program is written. The extended address can be the address of an output or input port, a register in a timer/counter, or any address used by the microprocessor. In these lessons, we will use the “$$” symbol to indicate the extended addressing mode. Remember it as two hex 8-bit bytes which make a 16 bit word; eg, ADD $$, AND $$, ORA $$, EOR $$, LDA $$, STA $$ and LDX $$. The instruction set in Table 1 is presented in various forms. The MC68HC705C8 technical summary has the instruction set on page 30. It shows the mnemonics, addressing modes, op-code and number of bytes in a form similar to Table 1. It also shows the number of cycles each instruction takes to execute. Other Motoro­la publications show the instruction set in different forms again and the one you use is a matter of personal choice. As an exercise, try filling out Table 2 from the Motorola 6805 instruction set. If you want the number of cycles, you will need the MC68HC705C8 technical summary or some other 6805 in­struction set. This program, like most of the programs that are written for the MAL-4, starts at location $0030. This is the first RAM location – see page 18 of the manual for the memory map. This shows us all the memory locations in “map” form. We can determine which addresses are usable for RAM and where the input and output ports are, etc. Example program Let’s write a simple program to demonstrate the things we have covered so far. We will make the LEDs on the output port (port B) flash in an inward pattern at 0.5-second intervals. The first (and most important) task is to write a flow chart – see Fig.1. It shows us what to do in picture form. The steps for the program are as follows: (1). Turn off all the LEDS at the output port. (2). Wait for 0.5 seconds. (3). Turn on the four outside LEDs at the output port. (4). Wait for 0.5 seconds. (5). Turn on all the LEDs at the output port. (6). Wait for 0.5 seconds. (7). Go back and do it all again. Writing the code Program sheet Fig.1: the flow chart for our example program. The program first turns on the four outside LEDs at the output port, then waits 0.5 seconds before turning on the remaing four LEDs. The program has been written on the MAL-4 program sheet – see Table 3. A blank copy of this sheet comes with the MAL-4 manual and you should photocopy as many as you need for writing programs. An explanation of each column follows: Address: the address where the program is to be written. Code: the 1, 2 or 3 bytes of machine code. Label: A place for notes and program entry positions. Mnemonic: the instruction mnemonic. Operand: the operand byte or address. Comment: a place to write plain English comments. The first part of the program (comment box 1) is a load/store operation. The load part uses the mnemonic LDA. We want to clear the output port, so we load the accumulator with $00. Because this is known, we will use the Immediate addressing mode. If we look up the code for LDA # (immediate), it is $A6 and it is a 2-byte instruction. The first byte is $A6 and the second byte is $00 (because we want to load the accumulator with $00). The address location is then incremented by two to become $0032. In the Store part of the operation, the mnemonic used is STA. We want to store the contents of the accumulator at the output port (Port B). A look at the memory map shows port B at memory location $0001. Since this address is known, we use the Extended addressing mode. If you look up the code for STA $$ (Extended) it is $C7 and it is a 3-byte instruction. The second and third bytes are the address of the memory location, so it becomes C7 00 01. The address is now in­crement­ed by three and becomes $0035. Silicon Supply and Manufacturing 74HC11 $0.45 74HC27 .40 74HC30 .40 74HC76 .55 74HC86 .45 74HC138 .85 74HC139 .50 74HC154 3.15 74HC165 .85 74HC174 .65 74HC373 1.05 74F00 74F02 74F08 74F10 74F11 74F20 74F21 74F27 74F30 74F32 74F36 .40 .40 .40 .40 .40 .40 .40 .40 .40 .40 .85 74F38 74F151 74F163 74F169 74F175 74F241 74F244 74F257 74F258 74F353 74LS00 .65 .55 .70 1.92 .65 .95 .90 .60 1.80 1.45 .50 74LS01 74LS02 74LS03 74LS05 74LS11 74LS12 74LS13 74LS14 74LS20 74LS21 74LS27 MAIL ORDER SPECIALIST .50 .50 .45 .45 .50 .50 .85 .55 .55 .40 .40 74LS30 74LS33 74LS49 74LS73 74LS74 74LS83 74LS85 74LS90 74LS92 74LS109 74LS126 .40 .50 2.35 1.10 .45 .75 .60 .90 1.20 .90 .50 PO Box 92 Bexley North NSW Australia 2207 74LS138 74LS139 74LS147 74LS148 74LS151 74LS155 74LS158 74LS160 74LS164 74LS175 74LS191 Credit Cards welcome -Visa, Mastercard, Bankcard. Plus Sales Tax, packing and postage .60 .60 2.35 1.05 .50 .50 .70 .75 .75 .80 .80 74LS193 74LS196 74LS240 74LS241 74LS245 74LS257 74LS273 74LS366 74LS368 74LS373 74LS374 .80 1.35 .90 .95 .80 .60 .80 .55 .60 .80 .85 Ph.: (02) 554 3114 Fax: (02) 554 9374 After hours only bulletin board on (02) 554 3114 (Ringback). Let the modem ring twice, hang-up, redial the BBS number, modem answers on second call. October 1993  81 TABLE 1 Mnemonic Description Addressing Modes IMM DIR EXT IX0 IX1 IX2 ADC Add with carry INH A9 B9 C9 F9 E9 D9 ADD Add without carry AB BB CB DB EB DB AND Logical AND A4 B4 C4 F4 E4 D4 ASL Arithmetic shift left (same as LSL) 48 58 38 78 68 ASR Arithemtic shift right 47 57 37 77 67 BCC Branch if carry clear (same as BHS) BCLR 0 Clear bit 0 in memory 11 BCLR 1 Clear bit 1 in memory 13 BCLR 2 Clear bit 2 in memory 15 BCLR 3 Clear bit 3 in memory 17 BCLR 4 Clear bit 4 in memory 19 BCLR 5 Clear bit 5 in memory 1B BCLR 6 Clear bit 6 in memory 1D BCLR 7 Clear bit 7 in memory 1F BCS Branch if carry set (same as BLO) 25 BEQ Branch if equal 27 BHCC Branch if half carry clear 28 BHCS Branch if half carry set 29 BHI Branch if higher 22 BHS Branch if higher or same (see BCC) 24 BIH Branch if interrupt pin is high 2F BIL Branch if interrupt pin is low 2E BIT Bit test BLO Branch if lower (same as BCS) 25 BLS Branch if lower or same 23 BMC Branch if interrupt mask is clear 2C BMI Branch if minus 2B BMS Branch if interrupt mask is set 2D BNE Branch if not equal (to zero) 26 BPL Branch if plus 2A BRA Branch always 20 BRCLR 0 Branch if bit 0 is clear 01 BRCLR 1 Branch if bit 1 is clear 03 BRCLR 2 Branch if bit 2 is clear 05 BRCLR 3 Branch if bit 3 is clear 07 BRCLR 4 Branch if bit 4 is clear 09 BRCLR 5 Branch if bit 5 is clear 0B BRCLR 6 Branch if bit 6 is clear 0D BRCLR 7 Branch if bit 7 is clear BRN Branch never BRSET 0 Branch if bit 0 is set 00 BRSET 1 Branch if bit 1 is set 02 BRSET 2 Branch if bit 2 is set 04 BRSET 3 Branch if bit 3 is set 06 BRSET 4 Branch if bit 4 is set 08 BRSET 5 Branch if bit 5 is set 0A 82  Silicon Chip INH INH REL B5C BTB 24 A5 B5 C5 F5 E5 D5 0F 21 Mnemonic Description Addressing Modes INH INH INH IMM DIR EXT IX0 IX1 IX2 REL B5C BTB BRSET 6 Branch if bit 6 is set OC BRSET 7 Branch if bit 7 is set OE BSET 0 Set bit 0 in memory 10 BSET 1 Set bit 1 in memory 12 BSET 2 Set bit 2 in memory 14 BSET 3 Set bit 3 in memory 16 BSET 4 Set bit 4 in memory 18 BSET 5 Set bit 5 in memory 1A BSET 6 Set bit 6 in memory 1C BSET 7 Set bit 7 in memory BSR Branch to subroutine CLC Clear carry 98 CLI Clear interrupt mask bit 9A CLR Clear CMP Compare accumulator with memory COM Ones complement CPX Comapre index register with memory DEC Decrement EOR Exclusive OR ACC with memory INC Increment JMP Jump JSR Jump to subroutine LDA Load accumulator from memory A6 LDX Load index register from memory AE LSL Logical shift left (same as ASL) 48 58 LSR Logical shift right 44 54 MUL Multiply unsigned NEG Negate 40 50 NOP No operation ORA Inclusive OR ACC with memory ROL Rotate left 49 59 ROR Rotate right 46 56 RSP Reset stack pointer 9C RTI Return from interrupt 80 RTS Return from subroutine 81 SBC Subtract with carry SEC Set carry bit 99 SEI Set interrupt mask 9B STA Store accumulator STOP Enable IRQ, stop oscillator STX Store index register SUB Subtract SWI Software interrupt 83 TAX Transfer accumulator to index register 97 TST Test for negative or zero TXA Transfer index register to accumulator 9F WAIT Enable interrupt, stop processor 8F 1E AD 4F 43 4A 5F 3F A1 B1 A3 B3 53 33 5A C3 3A A8 4C C1 5C B8 C8 3C 7F 6F F1 E1 73 63 F3 E3 7A 6A F8 E8 D1 D3 D8 7C 6C BC CC FC EC DC BD CD FD ED DD B6 C6 F6 E6 D6 BE CE FE EE DE 38 78 68 34 74 64 30 70 60 FA EA 39 79 69 36 76 66 42 9D AA A2 BA CA DA B2 C2 F2 E2 D2 B7 C7 F7 E7 D7 B5 CF FF EF DF B0 C0 F0 E0 D0 7D 6D 8E A0 4D 5D 3D October 1993  83 Table 2 Opcode Mnemonic A. Mode No. Bytes No. Cycles A6 LDA IMM 2 2 LDA EXT SWI INH STA EXT JMP EXT 43 A3 11 Box 2 is the 0.5-second time delay. Microprocessors are de­signed to run very fast, so it is sometimes necessary to slow down their operation. We do this by making them count a large number down to zero and this requires a time delay loop. The MAL-4 has a number of time delays in its monitor pro­gram. They are in a form called subroutines. You use a subroutine by jumping to it and the program remembers the point to which it is to return. Subroutines and time delay loops will be covered in later lessons. Time delay subroutines The time delay subroutines in the MAL-4 use the accumulator to vary the length of the delay (delay x acc), so you must load the accumulator before jumping to the subroutine. The delay subroutines and their addresses are as follows: D10µs: Delay = 10µs x Accumulator – $1498 D100µs: Delay = 100µs x Accumulator – $14A1 D1ms: Delay = 1ms x Accumulator –$14BD D10ms: Delay = 10ms x Accumulator – $14D9 D100ms: Delay = 100ms x Accumulator – $14E6 D1sec: Delay = 1 sec x Accumulator – $14F3 D1min: Delay = 1 min x Accumulator – $1500 We want a 0.5 second delay so the D10ms delay subroutine will do. This box requires a load accumulator immediate (LDA #) and a Jump to SubRoutine extended (JSR $$). The op-code for LDA # is $A6. The second byte of code will need to be 50 in hex or $32, since 50 x the 100ms delay subroutine gives a delay time of 0.5ms. If you look up JSR extended, it is a 3-byte instruction and the op-code is $CD. The second and third bytes will be the high and low address bytes of the location of the D100ms subroutine, Table 3 ADDRESS CODE LABEL MNEMONIC OPERAND COMMENT 0030 A600 START LDA #$00 0032 C70001 STA $$0001 Clear accumulator & store at output 0035 A632 LDA #$32 0037 CD14D9 JSR $$14D9 003A A6C3 LDA #$C3 003C C70001 STA $$0001 003F A632 LDA #$32 0041 CD14D9 JSR $$14D9 0044 A6FF LDA #$FF 0046 C70001 STA $$0001 0049 A632 LDA #$32 004B CD14D9 JSR $$14D9 Set time delay 50 ($32) x ACC = 0.5 seconds 004E CC0030 JMP $$0030 Jump to start 84  Silicon Chip Set time delay 50 ($32) x ACC = 0.5 seconds Load accumulator & store at output Set time delay 50 ($32) x ACC = 0.5 seconds Load accumulator & store at output $14D9. Don’t forget that the address is incremented by one, two or three bytes as the instruction requires (in this case, it is incremented by three bytes – $37 + $3 = $3A). Box 3 is almost the same as box 1 but instead of clearing the output port, we now want to switch on the LEDs on bits 7, 6, 1 & 0. This pattern corresponds to 11000011 in binary or $C3 in hex. Box 4 is a 0.5-second time delay and is the same as box 2. Box 5 is almost the same as box 1 but instead of clearing the output port, we now want to switch on all the LEDs. This means that the immediate byte will be $FF (ie, 11111111 in binary). Box 6 is a 0.5 second time delay and is the same as box 2. Box 7 (which is not really a box) needs to be a jump in­struction. This tells the processor to jump to an address loca­tion, in this case to the start address ($0030). The mnemonic and addressing mode will be JMP $$ (Extended). If you look this up in the instruction set you will find it to be a 3-byte instruction with an op-code of $CC. The second and third bytes will be the high and low bytes of the destination address $0030. Load the program into the MAL-4 and run the program from location $0030. The output port LEDs should flash in the pattern described. If not, go back and check that the program has been entered correctly. Mode 2 (the disassemble) mode may help you find your mistake. Things to do (1). Rewrite the flow chart and the program to make the LEDs turn on in a smooth inward pattern. In other words, make the LEDs turn on one bit at a time instead of two. (2). Experiment with the time delay to give a better visual effect. (3). Rewrite the flow chart and the program to make a 8-bit “Kitt” scanner; ie, one LED on at a time switching from left to right and back again. This will take up lots of RAM and you may need to jump to the RAM located at $0150 (page 1) and back again. This done, try writing programs for other time delays and patterns. (4). Do further reading on instructions and addressing modes, especially if you can get detailed information on the 6805 instruction set from a SC Motorola text/reference book.