Fullscreen HTML5Med Res (??MB)HTML4

Advances in computer technology 133MHz Pentium processor now available In June 1995, Intel introduced the 133MHz version of the Pentium processor, the ninth in the series and with more than twice the performance of the original 60MHz Pentium released in March 1993. In this article, we give a technical background to the Pentium which will shortly be the mainstream processor in PCs. So fast has the Pentium become accepted in the marketplace that it is rapidly displacing 486 processors, to the extent that they are likely to disappear some time after 1996. By the end of this year, Intel expects that most PCs, portables and notebook computers will be using the Pentium, in either 75MHz or 90MHz versions, with the 100MHz, 120MHz and 133MHz processors being employed in high-end machines. While incorporating new features and improvements, the Pentium is ful- ly software compatible with previous members of the Intel microprocessor family. The Pentium processor incorporates a superscalar architecture, improved floating point unit, separate on-chip code and write-back data caches, 64-bit external data bus, and other features designed to provide high performance. In its 75, 90, 100, 120 and 133MHz versions, the Pentium has power management (SL technology) and multiprocessor support. The on-chip multiprocessor interrupt controller can support up to 16 processors. Intel offers a 273-pin pin grid array (PGA) package for the 60 and 66MHz processors and a 296-pin staggered pin grid array (SPGA) package for the higher clock speed versions. In recent years, developments in semiconductor design and manufacturing have made it possible to produce increasingly higher performing microprocessors in smaller sizes. Foremost among these has been the development of Bi CMOS (bipolar comple­mentary metal-oxide semiconductor) technology with track sizes of less than a micron (one millionth of a metre). This allows more transistors to be fitted on a chip. First generation Pentiums (60 and 66MHz) are implemented in 5V, 0.8 micron BiCMOS technology with 3.1 million transistors, while the 75MHz and higher Pentiums use 3.3V, 0.6 micron BiCMOS technology with 3.3 million transistors each. The 133MHz Pentium is implemented in 3.3V, 0.35 This photo shows the 296-pin staggered pin grid array (SPGA) package for the higher clock speed (75MHz and above) versions of the Pentium. Note that the chip is labelled with the clock speed and the iCOMP® benchmark speed figure. 14  Silicon Chip Fig.1: this graph shows the very fast market transition which has occurred with the introduction of the Pentium processor. The changeover from 286 to 386 processors (with the 386 becoming predomi­nant) took about four years and the changeover from 386 to 486 took about three years. By contrast, the changeover from 486 to the Pentium has been much faster at around 2½ years and the numbers are growing at a staggering rate too. micron BiCMOS technology with 3.3 million transistors. This has allowed a 50% reduction in the die area (compared to 0.6 micron chips) and also allows the significant increase in clock speed. By the way, while the clock speed is 133MHz, the external bus speed is 66MHz. The increase in the number of transistors has made it possible to integrate components that were previously external to the processor, such as maths coprocessors, caches and multi­ pro­ cessor interrupt controllers. Placing these components on-board the chip decreases the time required to access them and increases performance dramatically. Another way to decrease the distance between components and at the same time increase the speed at which they communicate is to provide multiple layers of metal for interconnection. Intel’s 0.35 micron BiCMOS technology uses four layers of metal interconnections. Intel’s microprocessor family In 1985, Intel introduced the 80386, a 32-bit microproces­sor that handled 3-4 million instructions per second (MIPS). Available in speeds ranging from 16MHz to 33MHz, the 80386 ad­ dresses up to 4 gigabytes of physical memory and up to 64 Tera­bytes (1012) of “virtual memory”, which allows systems to work with programs and data larger than their physical memory, by employing spare capacity on hard disc drives. The 80386 provided for multi­ tasking and the ability to create “virtual 8086” systems, each running in its own 1-megabyte address space. Like its predecessors, the 386DX microprocessor spawned a new generation of personal computers, which had the ability to run 32-bit operating systems and ever more complicated applications, whilst maintaining compatibility with previous members of the Intel family. In 1989, Intel shipped the 486DX microprocessor, which incorporated an enhanced 386-compatible core, a maths coproces­sor, cache memory and cache controller – a total of 1.2 million transistors – all on a single chip. Operating at an initial speed of 25MHz, the 486DX processor provided up to 20 MIPS. At its peak speed of 50MHz, the 486DX processor operated at up to 41 MIPS. By incorporating RISC principles, the 486DX was able to execute most instructions in a single clock cycle. With the 1992 introduction of the 486DX2 microprocessor, Intel increased the speed of the 486 family by as much as 100 percent. The DX2 used “clock doubling”, which allows the proces­sor to operate twice as fast internally as externally. At its current peak speed of 66MHz, the DX2 processor executes up to 54 MIPS. With the introduction of the first versions of the Pentium in March 1993, even higher levels of performance became avail­able. Pentium now offers seven performance levels and has been designed into mobile computers, mainstream desktop systems, work­stations and servers. The newest member of the family, the 133MHz Pentium, executes up to 219 MIPS – four times that of the 486DX2. Superscalar design For those familiar with the architecture of small micropro­cessors such as the Z8, 8051 or PIC series, the technology in the Pentium is something else again, and the terminology is pretty foreign too. The heart of the Pentium processor is its supersca­ lar design, built around two integer instruction pipelines, each capable of performing independently. The pipelines allow August 1995  15 rounding and writing of the result to the register file and Error Reporting. The FPU incorpo­rates new algorithms that increase the speed of common opera­ tions, such as ADD, MUL & LOAD, by a factor of three. Performance improvements iCOMP® Fig.2: the new 133MHz Pentium has about double the performance of the original 60MHz version, according to the iCOMP® index used by Intel for speed comparisons. the Pentium to execute two integer instructions in a single clock cycle, nearly doubling the chip’s performance relative to an Intel 486 chip at the same clock speed. The Pentium’s pipelines are similar to the single pipeline of the 486 but they have been optimised to provide increased performance. Like the 486’s pipeline, the pipelines in the Penti­um execute integer instructions in five stages: Prefetch, In­struction Decode, Address Generate, Execute and Write Back. When an instruction passes from Prefetch to Instruction Decode, the pipeline is then free to begin another operation. In many instances, the Pentium can issue two instructions at once, one to each of the pipelines, in a process known as “in­struction pairing”. In this case, the instructions must both be “simple”; the v-pipe always receives the next sequential instruc­tion after the one issued to the u-pipe. Each pipeline has its own ALU (arithmetic logic unit), address generation circuitry and interface to the data cache. While the Intel 486 microprocessor incorporated a single 8Kb cache, the Pentium features two 8Kb caches, one for instruc­tions and one for data. These caches act as temporary storage for instructions and data obtained from slower, main memory; when a system uses data, it will likely use it again. Fetching it from an on-chip cache is much faster than fetching it from main memo­ry. The Pentium’s caches are two-way 16  Silicon Chip set-associative, an im­provement over simpler, direct-mapped designs. They are organised with 32-byte lines, which allows the cache circuitry to search only two 32-byte lines rather than the entire cache. The use of 32byte lines, up from 16-byte lines on the Intel 486DX, is a good match of the Pentium’s 64-bit bus width with four-chunk burst lengths. When the circuitry needs to store instructions or data in a cache that is already filled, it discards the least recently used information (according to an “LRU” algorithm) and replaces it with the information at hand. The combination of instruction pairing and dynamic branch prediction can speed processor operations considerably. For example, a single iteration of the classic Sieve of Eratosthenes benchmark requires six clock cycles to execute on a 486. The same code executes in only two clock cycles on the Pentium. Improved floating point unit The floating point unit in the Pentium has been completely redesigned from the 486 FPU. It incorporates an eight-stage pipeline, which can execute one floating point operation every clock cycle. In some instances, it can execute two floating point operations per clock (when the second instruction is an Exchange). The first four stages of the FPU pipeline are the same as that of the integer pipelines. The final four stages consist of a two-stage Floating Point Execute, The Pentium’s architectural features, superscalar design, separate instruction and data caches, write-back data caching, branch prediction and redesigned FPU, enable the development of new applications software, in addition to improving the perfor­mance of current applications in a manner that is completely transparent to the end user. The external data bus to memory is 64 bits wide, doubling the amount of data that may be transferred in a single bus cycle compared to a 486. The Pentium supports several types of bus cycles, including burst mode, which loads large portions of data into the data cache in a single bus cycle. The 64-bit data bus allows the Pentium to transfer data to and from memory at least five times faster than the Intel DX4. Several instructions, such as MOV and ALU operations, have been hardwired into the Pentium, which allows them to operate more quickly. In addition, numerous microcode instructions exec­ ute more quickly due to the Pentium’s dual pipelines. Finally, the Pentium features an increased page size, which results in less page swapping in larger applications. Due to the architectural improvements of the Pentium pro­cessor family, the 133MHz Pentium’s performance is more than three and a half times that of the 66MHz DX2. Error detection Error detection is performed on two levels, via parity checking at the external pins and internally, on the on-chip memory structures (cache, buffers and microcode ROM). Where data integrity is especially crucial, the Pentium supports Functional Redundancy Checking (FRC). FRC requires the use of two Pentium chips, one acting as the master and the other as the “checker”. The two chips run in tandem and the checker compares its output with that of the master Pentium to assure that errors have not occurred. FRC results in error detection greater than 99%. The Pentium also has a built-in feature for testing the reli­ability of the chip. This tests 70% of the Pentium’s components upon resetting the chip and is an implementation of the IEEE 1149.1 standard (Test Access Port and Boundary Scan Architecture). 75, 90, 100, 120 and 133MHz Pentiums have fully static 3.3V BiCMOS process technology. The static design allows the clock frequency to be reduced to zero, where the processor uses very little power. Typical power consumption is 3-4 watts. Power management Notebook computers need to match desktop performance while constrained by mechanical and electrical design considerations. These considerations have driven the development and implementa­tion of Intel’s Voltage Reduction Technology. The external pins of the Pentium processor with Voltage Reduction Technology are powered at 3.3V, which allows the processor to communicate with existing 3.3V components in the system. The internal core of the processor operates at 2.9V, resulting in up to 30% power savings over its desktop counterpart. Conse­ quently, system vendors can design with higher performing Pentium processors without loss of battery life. Pentium processors for notebooks and subnotebooks are of­fered in two encapsulations, a 320-lead tape carri- The Pentium incorporates the same power management capabil­ities as the Intel 386SL, 486SL and SL Enhanced 486 processors. This operates at the system level, controlling the way power is used by the entire system, including peripherals, and at the microprocessor level. In the latter mode, the processor is put into a low power state during non-processor intensive tasks such as word processing, or into a very low power state when the computer is not in use (“sleep” mode). Intel’s SL technology centres around SMM (system management mode) to control power at the system level. This allows the microprocessor to slow down, suspend or completely shut down various system components to maximise energy savings. Special notebook features er package (TCP) for the 75MHz and 90MHz versions and a conventional stag­ g ered pin grid array (SPGA) package. Multiprocessor support The Pentium’s Advanced Programmable Interrupt Controller (APIC) can support up to 16 processors. This supports symmetric multiprocessing, meaning that all processors appear equal to the operating system. Multiprocessor operating systems such as Wind­ows NT, OS/2 and new UNIX implementations use the symmetric multiprocessor model. Pentiums also include a dual processor mode which enables two processors to share a single second-level cache in a low-cost multiprocessor system. Pentiums include on-chip logic to maintain cache consistency between the two processors and to arbitrate for the common bus to the second-level cache. The on-chip APICs handle interrupts. A single processor desktop or server system design can be made multiprocessor ready by adding a second sock­et, an I/O APIC to the chipset SC and a few BIOS changes. ANOTHER GREAT DEAL FROM MACSERVICE 100MHz Tektronix 465M Oscilloscope 2-Channel, Delayed Timebase VERTICAL SYSTEM Bandwidth & Rise Time: DC to 100MHz (-3dB) and 3.5ns or less for DC coupling and -15°C to +55°C. Bandwidth Limit Mode: Bandwidth limited to 20MHz. Deflection Factor: 5mV/div to 5V/div in 10 steps (1-2-5 sequence). DC accuracy: ±2% 0-40°C; ±3% -15-0°C, 40-55°C. Uncalibrated, continuously variable between settings, and to at least 12.5V/div. Common-Mode Rejection Ratio: 25:1 to 10MHz; 10:1 from 10-50MHz, 6cm sinewave. (ADD Mode with Ch 2 inverted.) Display Modes: Ch 1, Ch 2 (normal or inverted), alternate, chopped (250kHz rate), added, X-Y. Input R and C: 1MΩ ±2%; approx 20pF. Max Input Voltage: DC or AC coupled ±250VDC + peak AC at 50kHz, derated above 50KHz. HORIZONTAL DEFLECTION Timebase A: 0.5s/div to 0.05µs/div in 22 steps (1-2-5 sequence). X10 mag extends fastest sweep rate to 5ns/div. Timebase B: 50ms/div to 0.05µs/div in 19 steps (1-2-5 sequence). X10 mag extends maximum sweep rate to 5ns/div. Horizontal Display Modes: A, A Intensified by B, B delayed by A, and mixed. CALIBRATED SWEEP DELAY Calibrated Delay Time: Continuous from 0.1µs to at least 5s after the start of the delaying A sweep. Differential Time Measurement Accuracy: for measurements $900 of two or more major dial divisions: +15°C to +35°C 1% + 0.1% of full scale; 0°C to +55°C additional 1% allowed. TRIGGERING A & B A Trigger Modes: Normal Sweep is triggered by an internal vertical amplifier signal, external signal, or internal power line signal. A bright baseline is provided only in presence of trigger signal. Automatic: a bright baseline is displayed in the absence of input signals. Triggering is the same as normal-mode above 40Hz. Single (main time base only). The sweep occurs once with the same triggering as normal. The capability to re-arm the sweep and illuminate the reset lamp is provided. The sweep activates when the next trigger is applied for rearming. A Trigger Holdoff: Increases A sweep holdoff time to at least 10X the TIME/DIV settings, except at 0.2s and 0.5s. Trigger View: View external and internal trigger signals; Ext X1, 100mV/div, Ext -: 10, 1V/div. Level and Slope: Internal, permits triggering at any point on the positive or negative slopes of the displayed waveform. External, permits continuously variable triggering on any level between +1.0V and -1.0V on either slope of the trigger signal. A Sources: Ch 1, Ch 2, NORM (all display modes triggered by the combined waveforms from Ch 1 and 2), LINE, EXT, EXT :-10. B Sources: B starts after delay time; Ch 1, Ch 2, NORM, EXT, EXT :-10. Optional cover for CRT screen – $35 through the vertical system. Continuously variable between steps and to at least 12.5V/div. X Axis Bandwidth: DC to at least 4MHz; Y Axis Bandwidth: DC to 100MHz; X-Y Phase: Less than 3° from DC to 50kHz. DISPLAY CRT: 5-inch, rectangular tube; 8 x 10cm display; P31 phosphor. Graticule: Internal, non-parallax; illuminated. 8 x 10cm markings with horizontal and vertical centerlines further marked in 0.2cm increments. 10% and 90% for rise time measurements. Australia’s Largest Remarketer of markings Graticule Illumination: variable. Beam Test & Measurement Equipment Finder: Limits the display to within the graticule area and provides a visible 9500; Fax: (03) 9562 9590 display when pushed. X-Y OPERATION Sensitivity: 5mV/div to 5V/div in 10 steps (1-2-5 sequence) MACSERVICE PTY LTD 20 Fulton Street, Oakleigh Sth, Vic., 3167. Tel: (03) 9562 **Illustrations are representative only. Products listed are refurbished unless otherwise stated. August 1995  17