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ails t e D t i u rc Pt.2: Ci Build a VGA digital oscilloscope One of the real attractions of this digital scope, based on a VGA monitor, is that you don’t have to peer at the display – it is large, bright and the different coloured traces and graticule make it easy to interpret what’s happening. In this article we discuss the circuit details. By JOHN CLARKE To fully understand the discussion, it will be a help if you can refer to the block diagram presented on page 28 of last month’s issue. The circuit for the VGA Oscilloscope has been split into two sections. The main section is Fig.1, on pages 66 and 67, comprises most of the circuit 20  Silicon Chip while the timebase circuit, Fig.3, is shown on page 69. 28 ICs are used in the entire circuit. However, as we shall see, some of the circuit is repetitive (for the CH1 and CH2 inputs) and much of it involves timers and counters. Looking at the top righthand corner of the two-page cir­cuit, S1 is the AC/ DC coupling switch for the Channel 1 input. S1 also has a GND setting to allow the trace to be positioned on the graticule as a ground (zero) reference point. Following S1, the input signal passes via the atten­uator switch S2. This is essen­tially a string of resistors, with each one by­passed by a capacitor to improve high freq­uency response. Trimmer capac­ itor VC1 allows adjustment of the frequency compensation. After the attenuator, the signal is applied to the gate of JFET Q1 which acts as a high impedance buffer. Its gate is pro­tected from excessive signal excursion by two back-to-back LEDs. These begin to conduct for signals in PARTS LIST 1 plastic case, 262 x 189 x 84mm, with metal panel 1 front panel label, 252 x 76mm 1 PC board, code 04307961, 252 x 75mm 1 PC board, code 04307962, 213 x 142mm 1 PC board, code 04307963, 252 x 75mm 2 PC boards, code 04307964, 20 x 32mm 3 2P3W slider switches (S1,S3,S11) 3 1-pole 12-way rotary switches (S2,S4,S5) 5 SPDT toggle switches (S6,S7,S8,S9,S12) 1 SPDT centre-off switch (S10) 2 10kΩ horizontal mount trimpots (VR1,VR3) 1 5kΩ horizontal trimpot (VR6) 2 500Ω linear pots (VR2,VR3) 1 5kΩ linear pot (VR5) 2 2-47pF miniature trim capacitors (VC1,VC2) 1 9-68pF miniature trim capacitor (VC3) 1 4MHz parallel resonant crystal (X1) 1 15-pin VGA line socket and lead 1 cable clamp 1 5mm rubber grommet 1 DC panel socket 2 BNC panel sockets 5 3mm LEDs (LEDs 1-5) 3 15mm OD black knobs 3 18mm OD knobs (1 green, 1 blue, 1 red) 92 PC stakes 2 8-way pin headers 1 1.8m length of 0.8mm tinned copper wire 1 150mm length of shielded cable 1 800mm length of 4-way rainbow cable 1 400mm length of red hookup wire 1 400mm length of green hookup wire 1 400mm length of blue hookup wire 1 400mm length of yellow hookup wire 1 400mm length of black hookup wire 3 3mm diameter x 6mm machine screws and nuts excess of ±1.8V peak and are there mainly to cater for the situation where the input attenuator is set too low for the size of the signal. Normally, if the attenuator is correctly set, the signal at the gate of Q1 will not exceed about ±200mV peak. IC1 and IC2 invert and amplify the signal by about 25 times to produce sufficient level for the following A-D converter which requires 5V for full conversion. VR2 controls the DC output offset of IC1 and IC2 and thereby has the effect of shifting the signal Semiconductors 4 CA3140 op amps (IC1,IC2, IC7,IC8) 2 ADC0820CCN 8-bit A-D converters (IC3,IC9) 2 MCM6206DJ20 20ns 8-bit RAMs (IC4,IC10) 4 74HC85 4-bit magnitude comparators (IC5,IC6,IC11, IC12) 4 7555,TLC555CN CMOS timers (IC13,IC20,IC22,IC28) 4 74HC74 dual D-flipflops (IC14,IC19,IC26,IC27) 1 74HC86 quad EXOR gate (IC15) 1 74HC4053 analog CMOS switch (IC16) 2 74HC193 4-bit presettable counters (IC17,IC18) 1 LM319 dual comparator (IC21) 2 74HC00 quad NAND gates (IC23,IC29) 2 74HC4040 binary counters (IC24,IC25) 1 7812 12V regulator (REG1) 1 7805 5V regulator (REG2) 2 2N5484 JFETs (Q1,Q2) 3 BC338 NPN transistors (Q3,Q6,Q9) 2 BC548 NPN transistors (Q4,Q7) 2 BF199 NPN RF transistors (Q5,Q8) 21 1N914 signal diodes (D1D16,D21-D25) 4 1N4004 diodes (D17-D20) 5 3mm red LEDs (LED1-5) Capacitors 1 1000µF 16VW PC electrolytic 1 33µF 16VW PC electrolytic 15 10µF 16VW PC electrolytic 1 6.8µF 16VW PC electrolytic 1 1µF 16VW PC electrolytic 2 0.22µF MKT polyester 14 0.1µF MKT polyester 1 .047µF MKT polyester 4 .0039µF MKT polyester 2 .0015µF MKT polyester 5 .001µF MKT polyester 2 680pF MKT polyester or ceramic 1 560pF MKT polyester or ceramic 1 470pF MKT polyester or polystyrene 2 390pF ceramic 2 150pF ceramic 2 82pF ceramic 3 47pF ceramic 2 22pF ceramic 3 3-60pF trimmer capacitors (VC1-VC3) Resistors (0.25W, 1%) 1 10MΩ 1 20kΩ 1 3.9MΩ 2 12kΩ 1 2.2MΩ 6 10kΩ 1 820kΩ 3 7.5kΩ 2 510kΩ 1 6.8kΩ 1 390kΩ 1 3.9kΩ 2 240kΩ 1 3.3kΩ 1 220kΩ 5 2.7kΩ 1 150kΩ 11 2.2kΩ 2 130kΩ 2 1.8kΩ 3 100kΩ 1 1.5kΩ 1 82kΩ 7 1kΩ 2 75kΩ 2 330Ω 2 51kΩ 1 220Ω 2 47kΩ 1 120Ω 3 39kΩ 3 75Ω 2 27kΩ Miscellaneous Solder, four self-tapping screws, cable ties. Fig.1 (following page): the main circuit section for the VGA Oscilloscope. This comprises the input circuitry, A-D converters (IC3 & IC9), memory storage devices (IC4 & IC10) and the oscilloscope timebase circuitry (IC13-15, IC17 & IC18). August 1996  21 22  Silicon Chip August 1996  23 Fig.2: these oscilloscope waveforms show the timing for the record sequence. The top trace is the read/write input of the A-D converters, while the middle trace is the enable input for the memory. The lower trace is the clock input to counter IC17. trace up or down the VGA screen. VR1, in the feedback loop for IC2, changes the gain for the vertical calibration function. Note that any change in the setting of VR2 will affect the overall gain of IC1 and IC2 since this is part of the gain set­ting resistance. However, the range over which the poten­tiometer is adjusted to set the waveform fully up or fully down on the screen is only a small percentage change compared to the overall resistance value. As a result, the gain change in not perceivable on the screen. IC1 and IC2 are powered from 12V in order to ensure an output swing capability of more than 5V, while diodes D1-D3 clamp IC2’s output to prevent overload in the following A-D converter. IC3 is an 8-bit high speed A-D converter with an inbuilt sample and hold feature. It has a 4-bit flash converter which uses 32 comparators to speed up conversion and can convert an analog signal to an 8-bit digital code in a maximum of 1.5µs. AD conversion is started by a low on the WR-bar input at pin 6 of IC3. This must be low for at least 600ns before going high and must remain high for a minimum of 800ns before the data is valid. The data output lines are connected to the RAM chip IC4. This is a 20ns access time high speed memory containing 32K bytes. We have only used 256 bytes and although this may seem wasteful, its selection was based on the high speed and cost. Paradoxically, 24  Silicon Chip larger memory can be less expensive than the less popular smaller RAM chips. High speed RAM is paramount for this application. Remember that when the memory is called to cycle through each location when displaying the stored waveform on the screen, the allotted time per memory location is only 125ns (4MHz rate or 250ns period and 125ns per half cycle). This means that there are 20ns devoted to accessing the correct data and 105ns devoted to comparing this value with the line counter. Any standard 120ns memory would be lost trying to keep up this pace. Channel 2 signals The signal process for channel 2 is identical to that de­scribed above, the path being via attenuator switch S4, buffer Q2 and amplifiers IC7 and IC8. A-D conversion is in IC9 and the data is stored in RAM chip IC10. IC17 and IC18, which are synchronous 4-bit preloadable coun­ters, drive the address lines of IC4 & IC10. The clock input at pin 5 of IC17 (which is also the A0 input for IC4 and IC10) is from IC16 at pin 4. When the oscilloscope is in display mode the clock signal comes from the MAGnification selection at S11a via pin 5 of IC16 and is fed through to pin 4. When in the record mode, the clock is from IC15c at pin 3 of IC16. This indirectly obtains a clock signal from the timebase oscillator, IC13. Triggering The outputs of IC2 and IC8 connect to switch S6 and this selects the source of triggering from channel 1 or channel 2. Comparators IC21a and IC21b take the signal from S6 to generate the trigger signal. IC21a generates trigger signals for positive-going signals while IC21b acts as an inverter to generate trigger signals for negative-going inputs. The trigger threshold (level) is set by VR5. Positive or negative triggering is selected by switch S7. The comparator output selected by S7 triggers IC22 which is a 7555 timer set up as a one shot. When triggered, its output at pin 3 goes high and remains high until reset by the update oscil­lator IC20. This occurs when S8 is in the realtime position but IC22 remains set if left in the store position. IC20 is another 7555 timer which operates as a free running oscillator. It charges the selected capacitor at pin 2 and 6 via a 6.8kΩ resistor and diode D7 and discharges it via the 150kΩ resistor. With this setup, its pin 3 output is high for a short time (to reset IC22) and low for a relatively long time to allow triggering from IC21. Flipflop IC19b is triggered either by IC22 or IC20, depend­ing on the setting of switch S9. In the free run position of S9, the display is updated at a regular interval set by the frequency of IC20. This means that the display will not be locked (ie, it will be moving) since a different part of the waveform will be stored at each trigger point. The triggered selection for S9 provides a static display since the waveform is stored at the same point in the waveform each time and only when the pin 3 output of IC20 is high. IC19b is reset when power is first applied, due to the 10µF capacitor at the cathode of D11 being discharged. This pulls the CLR input (pin 13) low to reset the Q output low and the Q-bar output high. When IC19b is triggered, Fig.3 (right): the VGA timebase circuit. NAND gate IC23a and X1 form a master crystal oscillator, while binary counters IC24 & IC25 provide the 8-bit data signals for IC5, IC6, IC11 & IC12 (on Fig.1). August 1996  25 Fig.4: these oscilloscope waveforms show the line sync pulses (top) and the frame sync pulses (bottom ). The centre trace is actually a horizontal line for the graticule. the Q output at pin 9 goes high and operates the three switches inside IC16 via the A, B and C inputs. This switches pin 4 to pin 3, pin 15 to pin 1 and pin 14 to pin 13. At the same time, the low output at pin 8 of IC19b (Q-bar) selects the ADC chips IC3 and IC9 (via their the CS inputs) and places IC4 and IC10 (RAM) in the write mode. The low Q-bar output from pin 8 of IC19b also clears IC19a, via the 560pF capacitor connected to pin 1. This causes the Q-bar output of IC19a to go high. Before this happens, the previously low Q-bar output of IC19a presets IC17 and IC18, via IC16. Diode D12 holds the C preset input (pin 10) of IC17 low and so both counters are preset to 0000 0000. An RC delay from the Q-bar output of IC19a to pin 13 of IC16 is used to extend the preset time for IC17 and IC18. The above sequence sets the circuit in the record mode. Timebase oscillator IC13 now controls the read/write inputs of A-D converters IC3 and IC9. Fig.2 shows a screen printout of oscilloscope waveforms of the timing for the record sequence. The top trace is the read/write input of the A-D converters. When low, the A-D con­verter samples the data and flash converts the four most signifi­ cant digits. 800ns after the rising edge of the read/write input, data from the A-D converter is valid. The middle trace of the oscilloscope waveform is the enable input for the 26  Silicon Chip memory. It is derived from the time­ base and passes through EXOR gate IC15a (IC15 is near the lower right­hand corner of the circuit, Fig.1). IC15a has its pin 1 input directly connected to the timebase, while pin 2 is connect­ed via an RC delay. Whe­ never the input to IC15a changes, pin 3 goes high for the delay period to disable the memory. This prevents any false data from the A-D converter being applied to the data inputs of the memory. The lower trace on Fig.2 is the clock input to counter IC17 which is a divide-by-two timebase signal. The timebase clocks IC14, which is connected as a toggle flipflop. Its output is passed through two EXOR gates, IC15b & IC15c, wired as non-inverters to introduce a small amount of delay between the posi­tive edge of the timebase and the change in the clock signal for IC17. This ensures that the memory is disabled via IC15a (middle trace) before the address is changed. When counters IC17 & IC18 have reached a count of 256, the QD output at pin 7 of IC18 goes high and clocks D-flipflop, IC19a. This produces a low at the Q-bar (pin 6) output of IC19a and this presets IC17 & IC18. A low pulse to the CLR input of IC19b via the 680pF capacitor sets the Q output of IC19b low and Q-bar high. The high Q-bar output deselects A-D converters IC3 and IC9 and switches the IC4 and IC10 memories to read mode via the Writebar inputs at pin 27. The low Q output switches IC16 so that the clock input of IC17 and address line 0 of IC4 are controlled by the 4MHz to 1MHz inputs at pin 5. These inputs come from the timebase circuit (see Fig.3). Also the memories are permanently enabled via the now low E-bar inputs caused by pin 15 of IC16 connecting to the low pin 2. Counters IC17 and IC18 are now preset by the line sync signal now present at pin 14. In addition, the low Q-bar output of IC19b clears IC19a via the 560pF capacitor connected to pin 1. Its Q-bar is high and so diode D12 connecting to the C input of IC17 is reverse biased. This input is pulled high via the 10kΩ resistor when S11b is in position 1. Preloading of IC17 now sets it to an initial count of 8. This may appear unusual, however it is used to move the oscil­loscope trace along the screen so that the trigger point is exactly in line with the far left graticule vertical line. Magnitude comparators IC5 and IC6 (top righthand corner of Fig.1) are digital magnitude compar­ ators with “less than”, “greater than” and “equal-to” outputs. For our application we only use the “equalto” output, pin 6, which turns on the display when the data from IC4 (channel 1 RAM) is identical to the line count from the VGA timebase circuitry. Pin 6 drives the base of transistor Q3 via a 2.2kΩ resistor. This is level-clamped using diode D13 and the 1.8kΩ resistor. The emitter follower configuration of Q3 drives the video input (green) of the VGA monitor via a 75Ω resistor. Thus the channel 1 trace is green. Transistors Q4 and Q5 are for blanking the display when updating the A-D conversion and during the line sync pulse re­spectively. This prevents the trace from producing an unusual display or overscanning. Q6, Q7 and Q8 operate in the same manner as above for the channel 2 trace; ie, Q6 drives the red gun of the VGA monitor, while Q7 & Q8 are for blanking. Q6 is driven by pin 6 of IC12. IC11 & IC12 are the digital magnitude comparators for channel 2. Power Power for the circuit is derived from a 12VAC plugpack which is rectified using D17-D20 and filtered with a 1000µF capacitor. REG1 and REG2 provide the +12V and +5V supplies for the circuit. The 10µF capacitors at the output of each regulator prevent instability. There are also a number of 10µF and 0.1µF decoupling capacitors across the supply rails. VGA timebase The VGA timebase circuit is shown in Fig.3. NAND gate IC23a is the master crystal oscillator operating at 4MHz. A 10MΩ resis­tor between pins 11 and 12 biases the inverter into the linear mode. Crystal X1 oscillates across the inverter pins with the 22pF capacitors providing loading to prevent overtone oscilla­tion. IC23b inverts the clock signal and both this signal and the pin 11 output from IC23a is applied to the Data (pin 2) and the Preset (pin 4) inputs of flipflop IC26b. IC26b is a D-flipflop and the inverted level at the Data input is clocked through to the Q-bar output on the positive edge of the CK input at pin 3. When the preset is low, the Q-bar output is set low. Graticule generation IC24 is a binary counter with outputs from Q1-Q12. These are advanced on the negative transition of the clock input at pin 10. Its Q4 output runs at 250kHz and this is inverted with IC29a to clock IC26b. When Q4 goes low and when the Preset input of IC26b is high, the Q-bar output of IC26b goes high. As soon as the Preset goes low again after 125ns the Q-bar output goes low again. This output produces a vertical graticule line signal 125ns wide and is repeated at a 250kHz rate or every 4µs. This means that we have 8 vertical graticule lines in the allotted 32µs for each line. The vertical line signal drives buffer transistor Q9 via a 1kΩ resistor. The three series diodes limit the base drive to 1.8V and the emitter to 1.2V. The line sync pulses are derived using IC26a which works in the same manner as IC26b. When the Preset input at pin 10 is low, the Q output at pin 9 goes high when Q7 of IC24 goes low. The result is a 2µs (set by the Q3 output of IC24) low-going pulse at the Q output of IC26a. This occurs every 32µs as set by the Q7 output of IC24. Note that the use of IC23c to NAND the Q3 and Q4 outputs of IC24 before being applied to the Preset input of IC26a essentially shifts the line sync pulse so that it occurs before the first vertical grat­icule line. IC25 is a second binary counter to give us the requisite Q13-Q16 outputs. Note also that Q9-Q16 are the line counter outputs used for comparators IC5 and IC6 and IC11 and IC12. Similarly, the 4MHz, 2MHz and 1MHz outputs are used to clock the memories when in the playback mode, as selected by switch S11a. Frame sync pulses Frame sync pulses are derived in a similar way to the vertical graticule line and line sync pulses. Q16 from IC25 provides a 61Hz signal, while Q9 from IC24 gives a 64µs pulse width. The oscilloscope waveforms in Fig.4 show the line sync pulses (top trace) and the frame sync pulse (bottom trace). The centre trace is actually a horizontal line for the grat­icule. Note that it occu­pies an entire line height from one line sync pulse to another. IC28 is triggered by the Q13 output which occurs at eight times the frame frequency. This gives us a possible eight horizontal graticule lines. Unfortunately, this number does not result in a graticule in the centre of the screen. And a central graticule line is a very desirable oscilloscope feature. In order to obtain this, timer IC28 is used to delay the occurrence of each line so that one will actually be in the centre. The .047µF capacitor along with the 3.9kΩ resistor and trimpot VR6 set the delay at about 2048µs. The horizontal line signal from IC28 is inverted and clocked through IC27b for a horizontal line signal which is locked into the line sync pulse. The horizontal graticule line is also buffered by Q9 before being applied to the blue gun input of the monitor. This completes the circuit description. Next month we will present the construction details of the VGA SC Oscilloscope. TRANSFORMERS • TOROIDAL • CONVENTIONAL • POWER • OUTPUT • CURRENT • INVERTER • PLUGPACKS • CHOKES STOCK RANGE TOROIDALS BEST PRICES APPROVED TO AS 3108-1990 SPECIALS DESIGNED & MADE 15VA to 7.5kVA Tortech Pty Ltd 24/31 Wentworth St, Greenacre 2190 Phone (02) 642 6003 Fax (02) 642 6127 If you are seeing a blank page here, it is more than likely that it contained advertising which is now out of date and the advertiser has requested that the page be removed to prevent misunderstandings. Please feel free to visit the advertiser’s website: www.latrobe.edu.au/ August 1996  27