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Pt.10: More On UHF Sampling Scopes In this concluding chapter in our series on cathode ray oscilloscopes we discuss the diode bridge switches used in UHF sam­pling scopes, accurate feedback A/D converters & random equivalent time sampling. We also look at some of the applications of 50GHz scopes. By BRYAN MAHER Last month, we discussed the broad principles of equivalent time sampling. We saw that UHF sampling scopes dispense with input attenuators and, as a consequence, can only handle a very limited range of signal amplitude. Now let us continue with the circuit techniques used in these UHF scope samplers. Scopes using sequential equivalent time sampling don’t need fast sampling rates because they accumulate sufficient samples over hundreds or thousands of triggers and signal passes. But the faster the sampler runs, the sooner the signal and its changes will appear on the screen. One of the world’s fastest scopes, the Tektronix 11801, has a sampler which runs at up to 200kS/s. This demands an incredibly short sampling interval of only 10 femto­ seconds; ie, 10fs (1fs = one millionth of a nanosecond)! So how does this scope achieve such a short sampling time? We recall from the previous chapter that UHF oscilloscopes use an electronic sampler switch (IC2) right at the input termi­nal, as shown in the block diagram of Fig.1. Periodically, the strobe signal closes IC2 momentarily Fig.1: placing the sampler right at the input terminal allows the use of a lower bandwidth analog amplifier (A2), be­cause the sampler transforms the ultra-high input frequency down to a lower frequency at W. 66  Silicon Chip Fig.2: a 4-diode bridge acts as a sampler switch, because the voltage at B mirrors any voltage applied at A. Early systems used analog feedback. and during that very short sampling interval, the input signal quickly charges holding capacitor C1 through resistor R1. Next, the strobe signal opens IC2 and holds it open for typically 5µs. Capacitor C1 holds the charge, giving the A/D converter ample time to digitise the voltage sample. The result­ant digital word is then stored in RAM. CMOS switching gates are far too slow for this job, because in the “on” condition, they store a considerable charge of elec­trons. These take time to remove, to change the gate to the “off” condition. By contrast, gallium arsenide (GaAs) diodes trap very few electrons while conducting. The less electrons held within the semiconductor, the faster they can be swept out to change from the on condition to the off condition. Diodes as switches How are diodes used as switches? The answer lies in a bridge circuit devised in the 1950s, as shown in Fig.2. The input signal is fed in to point A. For the off condition (which is most of the time), the differential strobe drive X,Y is inactive and all diodes are biased off. They are held nonconducting (ie, reverse-biased) by the positive DC supply V+ applied through resistor R2 to point H and by the negative supply V- applied through R3 to point J. To take a sample, the strobe generator creates a very short negative pulse at X, sufficient to overcome the positive bias at H. Also it produces an equal but positive pulse at Y, enough to overcomes the negative bias at J. Now with J positive and H negative, all diodes slam into full conduction, passing DC current from J to H. But here is the vital idea. Provided all diodes are identi­cal, the forward voltage drops J-A, J-B, A-H, B-H are all equal. So the upward flowing currents force points A and B to be always at the same potential. If no analog signal is applied at A, then, by the circuit balance, A and B will be at zero potential. Now let’s apply some input signal at A. When the strobe drive jolts the diodes into conduction, the diode currents will still force B to have the same voltage as the input signal at A. We say that B mirrors whatever is applied to A. This voltage at B charges holding capacitor C1 through resistor R1. That’s equivalent to a closed switch between A and B, isn’t it? The moment the strobe drive at X and Y ceases, the four diodes instantly become nonconducting. A and B are now complete­ly isolated, equivalent to an open switch. Capacitor C1 holds the sample of the input voltage long enough for the A/D converter to digitise it and store it in RAM. Integrated GaAs diodes In all diode samplers, the diode forward voltage drops should be low and equal. And they must have identical fast switching times. For best results, Gallium Arsenide (GaAs) diodes are integrated on a thin film substrate. This Tektronix TDS820 scope has a passband from DC to 8GHz without the delay line. Maximum sampling rate is 50kS/s on both input channels. The A/D converter digitises all signals into 16,384 decision levels, using 14-bit digital words. This provides increased accuracy in maths calculations and smoother screen traces. Equivalent timebase speeds can be 20ps/div to 2ms/div. June 1997  67 Fig.3: digital feedback raises the sampler efficiency and compen­sates for non-linearities. To keep the large strobe drive signals out of the sample to the A/D converter, the positive and negative pulses at X and Y must be truly differential. They must have exactly the same amplitude (but be opposite in polarity) and must rise and fall precisely together. This is achieved by transformer T1. If the strobe pulses X and Y are exact mirror images of each other, T1 has no effect. But should the positive pulse at Y be smaller than the negative pulse at X, transformer action in T1 will raise the positive and diminish the negative, until they have equal but opposite am­plitudes. Similar action occurs should the pulse timings become unequal. The very short sampling interval (needed to sample ultra high frequencies) reduces the sampler efficiency. That means C1 holds a smaller charge and the lower sample voltage fed to the A/D converter results in errors and noise in its digital output. To raise sampler efficiency, manufacturers first used posi­tive analog feedback, which we show as FB on the righthand side of Fig.2. A feedback amplifier G charges capacitor C2 to a voltage greater than C1. So from point Z the A/D converter was fed by a voltage larger than the sample at B. But this system required critical adjustment and was somewhat nonlinear. Digital sampler feedback Great improvements resulted from the introduction of digi­tal feedback sampling systems in 1987 in the Hewlett Packard HP54120 oscilloscope. In Fig.3, the sampler bridge A-B is fol­lowed by a matched analog amplifier (A2) and a 12-bit A/D convert­er. This produces digital data at N which is fed to microproces­sor M. Software running in this computer dynamically adjusts the feedback loop to increase the system gain and Fig.4: in a two-diode sampler, an integrated GaAs diode pair deposits charges on holding capacitors CN and CP proportional to the analog signal at A. 68  Silicon Chip automatically compensate for sampler non-linearities. This more exact solution, expressed in a longer 14-bit digital word output from the computer at Z, is recorded in the RAM. No adjustments are necessary, as the system is automatically controlled by the software. A positive feedback system is formed by feeding this 14-bit data from Z to a 14-bit D/A converter which converts the output digital data back to an analog signal at P. This is fed back to the sample hold capacitor at W. That raises the efficiency of the sampler, allowing it to be placed right at the scope’s input terminal. This way the scope bandwidth is not diminished by any front end analog amplifiers. Two diode sampler Because two integrated diodes are easier to match than four, Hewlett Packard frequently uses a 2-diode sampling gate as shown in the block diagram of Fig.4. Normally both diodes are biased off by the supply voltage applied through R2 and R3. To take a sample, the differential strobe signal momentari­ly overcomes the back bias, driving the diodes into conduction with their forward impedances equal. In this state, the diodes deposit charges on holding capacitors CN and CP proportional to the voltage of the input analog signal at A. After the strobe pulse has gone, those two capacitors hold the differential sample voltage long enough for the A/D converter to digitise the sample and store the data in the RAM. As before in Fig.2, the equalising transformer T1 keeps the strobe pulses X and Y truly differential. Digital feedback, similar to that in Fig.3, raises Fig.5: the SAR A/D converter (a) generates a 14-bit digital word in IC2. IC4 converts this word back to analog voltage V2 for comparison with the input sample V1 in comparator IC1. IC2 then adjusts that digital word (b) until V1 = V2, within one LSB. June 1997  69 the sampler efficiency and corrects non-linearities. All feedback sampling systems require the input signal to be repetitive. For that reason, they can only be used in equival­ent time scopes and never in real-time oscilloscopes. Feedback A/D converters Fig.6: a delay line allows time for the trigger and strobe elec­tronics to operate so that sequential equivalent time scopes can display signals at or before the trigger point. As we noted in the previous chapter in this series, the sampling rate and bandwidth are related only in real-time scopes but not in equivalent time oscilloscopes which therefore may sample comparatively slowly. The sampling rates are usually between 40kS/s to 200kS/s. This gives them the luxury of more time to digitise the signal. Therefore 14-bit feedback type A/D converters may be used, giving much greater accuracy in maths calculations and smooth­er traces on the screen. Feedback A/D converters use a completely different approach to the digitisation process, compared to the flash converters we saw earlier in this series. But the input analog signal must be repetitive. SAR A/D converters Fig.7: the random sampler (a) free runs continually and the time between the trigger and each sample is recorded. The scope reas­sembles all those samples (b) into a display equivalent to the input signal. 70  Silicon Chip The Successive Approximation Register or SAR A/D converter is one favoured type, which we show in Fig.5(a). The signal sample, after amplification in A2 (in Fig.1), is now called V1. IC2 is the SAR or Successive Approximation Reg­ister, a complex integrated circuit which contains a microproces­sor control section and 14 parallel 1-bit programmable registers, one for each output bit. Bit 1 is the MSB (most sig­nificant bit) and bit 14 is the LSB (least significant bit). CLK is the system clock. In Fig.5(a), the 14-bit output digital word from the SAR goes via 14 parallel lines to an output latch IC3. This digital data also goes around in a feedback loop to a 14-bit D/A converter IC4, which reconverts that data into an analog voltage V2. This feeds into the positive input of comparator IC1. The output of IC1 is at logic 1 level if V2 > V1, or logic 0 if V2 < V1. The aim of a feedback A/D converter is easy to see. The computer within the SAR produces a 14-bit digital word and compares its reconverted equivalent value, V2, with V1 in IC1. As a result of that comparison, on each clock pulse the SAR modifies its 14-bit word to one that will reconvert in IC4 to a new value of V2, which is closer to V1. So, in stepwise fashion, the 14-bit digital word approaches the value which truly repre­sents the sample input V1, as we illustrate in Fig.5(b). Let’s look at just the first three steps in detail. Ini­tially, latch IC3 is disabled, to isolate the converter from the RAM. All 14 output registers are reset to logic 0. When the sampler has captured a sample, it also issues the start command (SC) to IC2. On the first clock pulse, the computer in the SAR (IC2) sets the bit 1 register (the MSB) to logic 1, giving digital word 10000000000000. D/A converter IC4 instantly converts this to V2 = 2.5V, as Fig.5(b) illustrates. Because V2 < V1, IC1’s output will be at logic 0, so bit 1 is accepted as correct. On the second clock pulse, the SAR sets bit 2 to logic 1, giving digital word 11000000000000. That converts in IC4 to V2 = 3.750V which is too large (ie, V2 > V1) – see Fig.5(b). Therefore the SAR resets bit 2 to logic 0, resulting in digital word 10000000000000. The third clock pulse now sets bit 3 to logic 1, producing digital word 10100000000000. IC4 immediately reconverts this to 3.125V, so V2 < V1. Therefore the computer accepts this bit as correct. This action continues, moving down one register at each clock pulse. It sets the next bit to logic 1 and compares the reconverted V2 with V1. That bit remains set to 1, unless the resulting V2 is too large, in which case it’s reset to 0. In this way, V2 approaches V1 in a sequence of successive approximations, as we see in Fig.5(b). After 14 clock pulses, the SAR has created a 14-bit digital word equivalent to the analog sample V1, accurate to within 1 LSB; ie, with an error of less than 5V/214 = 5V/16,384 = 0.000305V. Latch IC3 is then ena­bled, recording that digital word in the RAM. Now the scope accepts another trigger event; a new sample is taken, held, digitised, recorded and the whole process re­peats. From this we see why feedback A/D converters can’t run very fast. And of course, they require a repetitive signal. Delay lines When you trigger the scope inter- Fig.8: a time domain reflectometry (TDR) test (a) for faulty connections at H. Normally the terminated line (b) divides the signal down to 0.5V continuously. But an open circuit (c) at H raises the voltage at X to 1V at time t2. Or (d) a short at H drops the voltage to zero at t2. The product of time difference (t2-t1) and the signal velocity equals twice the distance from X to H. nally from some rising step (ie, the trigger edge part of your signal), you often want to display that section of the input waveform. But sadly, sequential equiv­alent time sampling oscilloscopes cannot directly display that trigger edge (and analog scopes can’t either). The reason is illustrated in Fig.6. All signals suffer a propagation delay of 2-18ns in passing through the trigger takeoff, timebase and strobe generator circuits. So with very fast signals, the rising edge which triggered the scope is gone before the first sample can be taken. To make the rising edge visible, the solution is to take the input signal directly to the trigger takeoff, at point T on Fig.6. The input signal must also be delayed by a few nanoseconds before it enters the sampler diode bridge switch at A. Ordinary 50Ω coaxial cable can provide the required delay, as signals travel in coax lines at about 66% of the speed of light in air; ie, 0.66 x 3 x 108m/s = 200mm/ns. So two metres of coax cable would give a signal delay of about 10 nanoseconds. Scope manufacturers market spe- cial delay cables which provide delays up to 25ns. Some have a spiral inner conductor construc­tion to slow the signal velocity, giving the required delay with a shorter length. Using these, many samples can be taken before, during and after that edge of the signal which initiated the trigger. It’s called displaying pretrigger information. Random equivalent sampling Some oscilloscopes use random, rather than sequential, equivalent time sampling. In this type of scope, the sampling bridge switch free-runs continuously, regardless of whether a trigger event occurs or not. Again we assume that the input signal is repetitive. If a trigger is applied to the scope’s external trigger terminal and it is in sync with the input waveform, then the scope sets about digitising and recording those samples. In Fig.7(a) we show six passes of the input signal, each associated with a separate trigger event T1, T2, T3, etc. On each pass, the scope takes one sample, S1, S2, S3, etc. The signal waveform period might be only 10ps June 1997  71 Eye diagrams are sequential traces of logic pulses. The amount of time jitter in the pulse train is indicated by the degree to which the centre eye is partially closed by fuzzy traces. in reality but triggers and samples are accepted at a much slower pace. This is because the scope must allow maybe 5µs or even 50µs for each A/D conversion. Each sample is digitised and the digital word which repre­ sents its amplitude is recorded in RAM. In addition, the time between each trigger and sample, such as t1 in the first pass, t2 in the second pass, etc, is also measured. The value of this time in picoseconds decides the address in memory in which that sample will be recorded. So each digital word held in RAM represents two pieces of information: the amplitude of the sample and its timing with respect to the trigger. In Fig.7(a) we see just a few samples for clarity. In reality, hundreds or thousands of samples are taken, digitised and recorded. When enough samples are accumulated in the RAM, the display processor assembles them all as many bright dots on the scope screen as we see in Fig.7(b). The vertical coordinate of each represents the amplitude of that sample and the horizontal posi­tion gives its timing with respect to the trigger. The combina­tion displays the equivalent signal waveform. But the free-running sampler is usually not in sync with either the input signal or the trigger. Therefore, sam- ples may be taken anywhere: before, during or after the trigger. Samples taken before the trigger give pretrigger information of the input signal without any need for delay lines. And because the sample timing is random with respect to the input signal phase, this type of scope is insensitive to alias­ing. However, there is a down side to random sam­pling. It’s quite possible for many samples to have the same timing measured from the trigger event. Of all the samples taken, suppose 20 of these occur with the same timing after the trigger. They will all be recorded in the same address in the RAM. So 19 of those samples and digitisations are redundant and a waste of processing time, as they all will represent the same point on the displayed trace. So the scope must take more samples to make up enough for a smooth display. And of course, the input signal must always be repetitive. Applications International telecommunications involves many satellites, each containing 15-50 transpon­ders operating in the Ku 14-12GHz band and relaying 40,000 phone conversations. All float in geostationary orbit 42,000km high above the Earth’s centre. They receive and retransmit strings of serial data generated by many different equipments in many countries. For all these to be compatible, international stan­ dards specify, amongst other things, how much time jitter in pulse trains is acceptable. The Tektronix 11801B 50GHz scope can be expanded to 136 input channels using plug-in sampling heads in bandwidths up to 50GHz and 7ps internal risetime. It supports predefined masks for eye diagram presentation. The SD24 plug-in sampling head produces a step voltage rising in less than 36ps for time domain reflectometry measurements. Equivalent timebase speed can be set to an incredible 1ps/div or it can be slowed down to 5ms/ div, in 1ps steps. 72  Silicon Chip One essential application of UHF scopes is to ensure com­pliance with these specifications. For this, communications engineers and technicians display strings of multiple superim­ posed digital pulses of their systems. They overlay many logic 1 and logic 0 pulses. Inevitably, in real very fast systems, the pulse jitters with respect to the clock and this is displayed as an eye pat­tern on the scope. The more jitter present, the less clear space remains in the “eye” of the diagram. Standard templates are also displayed on the screen. If the eye area within the template remains clear, meaning not too much jitter, then that transmis­sion will be accepted by the satellite. Time domain reflectometry Time Domain Reflectometry (TDR), another important applica­tion of fast sampling scopes, can find circuit faults by measur­ing signal reflection over picoseconds. In Fig.8(a) we see a 1V step signal, from a source A of output impedance RS = 50Ω. This feeds to some integrated circuit B which has an input impedance of RT = 50Ω. The connection from A to B is through a conductor pair which also has a characteristic im­ pedance of 50Ω. We should remember that at Gigahertz frequencies every wire is a transmission line. H may be a soldered joint on a board or a welded junction in leads within an integrated circuit. The 1V step occurs at time t1. Normally the source im­pedance RS and the terminating resistance RT form a voltage divider with a division ratio of 2, so the scope displays a constant 0.5V at point X as shown in Fig.8(b). Now let’s suppose the junction at H is faulty, leaving an open circuit at H. Initially, the 1V step at time t1 must charge up the conductor’s own self-capacitance. The conductor’s 50Ω characteristic impedance forms a voltage divider with the source RS, so at first the potential at X rises to only 0.5V as we see in Fig.8(c). That 0.5V step travels as a signal from X to H, charging up the line as it goes. When it reaches the open circuit at H, the conductor is now charged, so the voltage at H can rise to the full 1V. This new voltage step at H, from 0.5V to 1V, travels as another signal back from H to X, lifting the voltage along the line to 1V as it goes. Eventually it reaches point X at time t2 and only then does the scope display the voltage step up to 1V as shown in Fig.8(c). Signals travel in parallel conductors at velocities between 0.25mm/ ps to 0.29mm/ps. So from the time difference (t2 - t1) we can calculate the distance from X to the open-ended break at H and return. On the other hand, if the fault at H was a short circuit, the display on the scope would be like Fig.8(d). Only extremely fast sampling scopes can measure these picosecond time differ­enc­es. References: (1) HP 5952-0163 and Product Note 54720A-2. (2) Tektronix publications 85W-83061, 85W-8218-0, 85W-8308-0, 55W10416-2. (3) G. Caprara: Encl. of Space Satellites; Eng.trans.Bay. Acknowledgement: thanks to Tektronix Australia and Hewlett Packard Australia and their staffs for data and some of the illustrations. June 1997  73