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Colour TV pattern generator; Pt.1 This versatile colour TV pattern generator stores its patterns in a ROM which is programmed via a computer port. It’s easy to build and you can even customise it to include your own patterns. By JOHN CLARKE This new Colour TV Pattern Generator is a ground-breaking design for SILICON CHIP. It is the first circuit that we have produced that uses an EEPROM which you can program from your own PC. This means that if you don’t like the standard patterns, or have some special requirement, you can modify the software and program 14  Silicon Chip in your own patterns (provided you have Quick Basic). Of course, you don’t have to do this if you don’t want to. We anticipate that several retailers will offer this design as a complete kit of parts and will include a pre-programmed EEPROM. Pre-programmed EEPROMs will also be available from SILICON CHIP, as will the programming software. Basing the design on an EEPROM has a number of advantages. For the first time, it allows us to offer a circle as one of the patterns. Our previous designs have omitted this rather useful feature because it couldn’t be done with conventional logic circuits. The EEPROM approach simplifies the circuit and makes the unit easier to build. Using a pattern generator If you service colour TV sets or want to adjust your own TV set for a first class picture, a pattern generator is a must. It is an essential tool for making convergence and purity adjust­ments, for adjusting picture geometry and for fault finding. These screen images (captured via a PC video frame grabber) show just four of the patterns produced by the pattern generator (the others are red raster, white raster and greyscale). Note that the circle appears stepped because the image is not interlaced. Note also that the colours shown in the colour bar pattern are not true to life, due to limitations in the printing process. This unit can generate seven different patterns: checkerboard, dot, circle/crosshatch, red raster, white raster and colour bars. In addition, you can select between greyscale and colour patterns. We’ll look at each pattern in turn and describe how it’s used. First, the checkerboard pattern provides a useful indica­tion of the low frequency response of the video stages. If the set is functioning correctly, the black/white edges of this pattern will be sharp and straight. Conversely, a set with a poor low-frequency response will show smearing between the black and white areas, along with rounded corners. The dot and crosshatch patterns are useful when making static and dynamic convergence adjustments. On a set with poor static convergence, for example, each dot will actually consist of separate red, green and blue dots rather than a single white dot. Similarly, poor dynamic convergence will cause the lines in the crosshatch pattern to splay into separate red, green and blue lines at the edges of the screen. The crosshatch/circle pattern is also useful when adjusting picture geometry. This involves setting the correct height and width to obtain a perfect circle and minimising pincushion dis­tortion. “Pincushion distortion” refers to the tendency for lines near the edges of the picture to bend inwards or outwards at the centre. The red and white rasters (ie, full red and full white screens) allow purity adjustments, so that the entire screen shows the one colour without irregularities. On sets with purity problems, the white raster may show blotches or red, green or blue. This indicates that it is necessary to degauss (ie, demagnetise) the metalwork inside the picture tube. Eight colour bars – white, yellow, cyan, green, magenta, red, blue and black – make up the colour bar pattern. This pat­tern is ideal when tracking down faults, since any waveforms depicted on a TV set circuit diagram are typically staircases, usually derived using a colour bar pattern as the RF/video source. By comparing the observed waveforms with those depicted on the circuit diagram, it is often possible to locate the faulty section. By turning the colour burst off, we get a greyscale bar pattern ranging from white to black. This is used for checking the greyscale tracking and for brightness and contrast adjustments. Design improvements Our last Colour TV Pattern Generator was published in November 1991. Although it produced nominally the June 1997  15 Main Features •  Produces dot, crosshatch/circle, checkerboard, red raster, white raster, colour bars and greyscale •  Patterns correctly centred on the screen •  Square crosshatch and checkerboard patterns •  Direct video output plus RF video modulator output •  Option for S-video outputs (chrominance and luminance signals) •  Audio input for video modulator (to test sound) •  Patterns and sync stored in ROM with option to customise pat­terns Specifications Number of lines ����������������������������������� 312 (Aust. PAL Standard: 312.5 x 2) Line (H) sync ��������������������������������������� 4.57µs (Aust. PAL Standard: 4.5-4.9µs) Line period ������������������������������������������ 64.087µs (1358ppm fast) (Aust. PAL standard: 64µs) Line (H) blanking ��������������������������������� 12.22µs (Aust. PAL Standard: 11.8-12.3µs) Field (V) sync �������������������������������������� 7 lines (Aust. PAL Standard: 2.5H for preequalis­ing pulses, 2.5H for sync and 2.5H for post-equalising pulses) Field (V) blanking �������������������������������� 25 lines + 12.22µs (Aust. PAL Standard: 25 lines + 11.8-12.3µs) Field frequency ������������������������������������ 50.012Hz (2400ppm fast) (Aust. PAL Standard: 50Hz) Crosshatch pattern ������������������������������ 11 horizontal (1 line high) x 15 vertical lines (305ns wide). Horizontal and vertical lines are located at the screen centre Circle pattern ��������������������������������������� 80% of full vertical screen height, 60% of full horizontal screen. Dot pattern ������������������������������������������ 11 horizontal rows (1 line high) x 15 vertical col­umns (305ns wide). A dot is at the centre of the screen Checkerboard pattern �������������������������� 7 horizontal x 5 vertical squares alternate black and white Colour bar pattern ������������������������������� 8 vertical bars 6.1µs wide with 1.22µs extra width on outside bars Bar colours ������������������������������������������ standard white, yellow, cyan, green, magenta, red, blue and black Colour burst signal ������������������������������ 10 cycles of 4.43361875MHz signal occurring 5.59µs after beginning of H sync <at> 249mV p-p (Aust. PAL Stan­dard: 10 cycles 5.6µs after leading edge of H sync) RGB to YUV encoding ������������������������� Y = 0.299R + 0.587G + 0.114B, U = 0.493 (B-Y), V = 0.877(R-Y) – (to Australian PAL Standard) Chrominance to luminance delay �������� -170ns RF output channel ������������������������������� 0 or 1 Video output impedance ���������������������� 75Ω Video output ���������������������������������������� 2Vp-p unloaded, 1Vp-p with 75Ω loading 16  Silicon Chip same patterns as this latest version (but no circle), it did have a few minor drawbacks. First, the patterns were not centred exactly in the middle of the screen, which made convergence adjustments less precise. Second, the crosshatch and checkerboard patterns were not exactly square, which made it harder to check for linearity errors in the picture. Third, it used a Philips TEA­ 2000 colour encoder IC which is now obsolete. These drawbacks have all been overcome in this new design. As mentioned above, the new circuit uses an EEPROM (electrically erasable programmable read only memory) to store all the patterns and generate the sync pulses. This arrangement reduces the IC count from 16 to 11 and correctly centres the patterns on the screen. In addition, the checkerboard, crosshatch and dot patterns are exactly square and a circle has been added, as noted above. The circle allows screen linearity to be checked at a glance and makes for straightforward height/width adjustments. If the circle is looking a little squat, for example, then the height is too low. Conversely, if the circle looks tall and thin, the height needs to be reduced. Most of the signals from the Colour Television Pattern Gen­erator comply with Australian PAL standards. These include the horizontal sync pulse and blanking intervals, and the colour burst and its position. The vertical sync pulse signal does not include the pre- and post-equalising pulses since these are only necessary with an interlaced 625-line signal. Physical arrangement The SILICON CHIP Colour Pattern Generator is housed in a standard plastic instrument case and is powered from a 12VAC mains plugpack. A 5-position rotary switch selects between the checkerboard, dot, crosshatch/circle, red raster and white raster patterns, while a 2-way toggle switch is used to select the colour bar pattern. An adjacent toggle switch selects either the colour and greyscale patterns, while a third toggle is the power on/off switch. Both composite video and RF outputs are provided on the rear panel (RCA sockets) and there is also an audio input socket. The latter allows audio to be fed directly into the RF Fig.1: this block diagram shows the unit in pattern mode. There are three main circuit sections: (1) an oscillator (clock) stage comprising IC6a, IC6b & crystal X1; (2) counters IC2-IC5; and (3) memory IC1 (the EEPROM). The oscillator clocks the counters which in turn drive address lines A0-A15 of the memory IC. The various patterns stored in IC1 appear at the data out­puts (D0-D7). Fig.2: block diagram of the AD722 RGB-to-PAL colour encoder IC. This IC accepts RGB and sync input signals and produces both composite video and S-video (separate chrominance and luminance) signals at its outputs. June 1997  17 (IC10). IC11 detects when the memory has reached the end of one field. It then resets the counters and the pattern starts all over again. Switch S2 selects between the patterns on D0-D3, while S3 and IC8 select between this and the colour bar signal on D4-D6. The selected RGB signal is buffered using IC9 and attenuated to a 0-700mV signal before being fed to the RGB-to-PAL encoder (IC10). IC10 produces a composite video output and a separate luminance signal. Switch S4 selects the composite video output from IC10 for colour video and the luminance output for greyscale video. The resulting signal is then made available as direct video. It is also applied to a video modulator to produce a modulated RF signal on VHF channel 0 or 1. An audio signal can also be applied to the RF modulator if required although this facility is not normally provided in a pattern generator. RGB-to-PAL encoder Fig.3: this is the block diagram of the unit when it is configured to programming mode (by changing some on-board jumper pins). Each address in the mem­ory is programmed by applying the correct level to the data lines (D0-D7) and then applying a short pulse to the E input of IC1 modulator and this can be useful when tracing audio problems in a TV set. In addition, S-video outputs can be added if required by connecting appropriate leads to the luminance and chrominance pins on the PC board. Operating modes Because it is a programmable device, this new pattern gen­ erator can be configured to operate in two modes: (1) programming mode; and (2) pattern generator mode. These two modes are select­ed by means of five jumpers on the PC board. Selecting the programming mode (by moving all the jumpers to the front pins of their 4-pin blocks) allows the EEPROM to be programmed via the PC’s parallel port and an on-board DB25 con­nector. Once programming has been completed, the jumpers are reset so that the unit can function as a pattern generator. The software for programming the EEPROM is written in Quick Basic, which originally came with DOS 5. The data stored in the EEPROM is arranged in lines which directly cor18  Silicon Chip respond to the lines displayed on the TV screen. This means that you can edit an existing pattern line-by-line to produce a custom display, if required. Block diagram Refer now to Fig.1 for a block diagram of the unit (pattern generator mode). It might look complicated but we’ll go through the various stages in turn and explain how it all works. Three main circuit sections are required to produce the requisite patterns: (1) an oscillator (clock) stage comprising IC6a, IC6b & crystal X1; (2) counters IC2-IC5; and (3) memory IC1 (the EEPROM). The oscillator stage clocks the counters which in turn drive the address lines (A0-A15) of the memory IC. The various patterns stored in IC1 appear at the data out­puts (D0-D7). Outputs D0-D3 provide the checker-board, dot, crosshatch/circle and raster signals, while D4-D6 provide the blue, green and red signals for the colour bar sequence. D7 produces the composite sync pulses and these are fed to the RGB-to-PAL encoder stage The RGB-to-PAL encoder is an Analog Devices AD722 16-pin surface mount device. It produces a top-quality PAL video signal from RGB and composite (horizontal and vertical) sync input signals, the latter fed from D7 of IC1. Fig.2 shows the block diagram of the AD722. This IC is rather complicated and, among other things, contains a phase lock loop (PLL) and various filters and delay lines. It requires no external components other than a crystal and a trimmer capacitor to set the colour burst frequency. The RGB inputs to the AD722 are each first passed through on-chip capacitors and clamped to the black level during the blanking interval. These three signals then pass into an analog encoding matrix to create the luminance (Y) and the U and V colour difference signals. After that, the Y signal passes through a 6MHz low-pass Bessel filter which prevents aliasing in the following sampled delay line. This delay line produces a 170ns difference between the luminance and chrominance signals. The delayed signal then passes through a 5MHz low pass filter to remove the sampled delay line artefacts. The U and V signals pass through 1.5MHz low pass filters to prevent Fig.4: this diagram shows the general arrangement of the blanking inter­vals and the visible screen area. The picture is made up of 312 lines which are scanned horizontally, one line at a time, from top to bottom. Note that lines 1-23 at the top of the screen and lines 311-312 at the bottom of the screen are not seen since they are reserved for field blanking aliasing in the following balanced modulator stages where the colour burst signals are injected. Note that the burst injec­ tion to the V signal is alternated between 90° and 270° at half the line rate to comply with the PAL standard. The outputs from the balanced modulators are then summed and fed to a 4.4MHz low-pass filter to remove any artefacts generated in the modulators. The resulting chrominance signal is summed with the lumi­nance output to produce composite video. In addition, the lumi­nance and chromin­ance signals are made available as separate outputs (S-video). The HSYNC and VSYNC inputs accept the sync signals. Either separate horizontal and vertical sync signals can be applied or a composite sync signal (as used in this design) can be applied to just one of these inputs. In either case, the following stages produce a composite sync signal and this is inserted into the luminance signal between the 3-pole low-pass filter and the sampled delay line. All other timing is generated by a 4 x 4.43MHz clock signal which can be derived from a 4.43MHz colour burst crystal or from a 17.734MHz crystal. When a 4.43MHz crystal is used, the IC is configured to multiply the frequency by four using the internal phase lock loop. Programming mode Fig.3 shows the block diagram for the unit when it is con­figured to programming mode. Three regulated supplies are required for programming. The 5V regulator provides most of the power for the ICs, while the 6V supply powers the memory which can be either an EEPROM or a One Time Programmable Read Only Memory (OTPROM). The 12.5V supply is used to provide the programming voltage. Basically, each address in the mem­ ory is programmed by applying the correct level to the data lines (D0-D7) and then applying a short pulse to the E input of IC1. Let’s look at this in greater detail. In practice, the programming process is controlled by the computer and the software which drives the Port A, Port B and Port C lines. There are several lines at work here: (1) the D2 Port C line – this applies the clock signal to the counters (IC2IC5), to increment the address of the memory; (2) the -D1 Port C line – this triggers the program pulse genera­tor IC7; (3) the D4 Port B line – this watches for the end of the program­ming pulse; and (4) the Port A lines – these drive the Data lines (D0-D7) of IC1. When power is first applied, the counters are reset to the first memory address of IC1. Data is then applied June 1997  19 to D0-D7 from Port A, after which D1 of Port C triggers the pulse generator to program the first memory location. At the end of the programming pulse, D4 of Port B signals the computer and the counter is clocked to the next count via D2 Port C and inverter IC6c. The next memory address of IC1 is now accessed and the relevant data again applied to D0-D7 and pro­grammed in. This sequence continues until all the data has been programmed in. EPROM coding Fig.5: this diagram shows, in graphical format, the programming codes for the various patterns which are programmed in via data lines D0-D7 for each line from 1-312. Note that all lines are high during the first 40 locations for line blanking and for lines 311-23 for field blanking. D7 is the sync signal and this is low for 15 locations (4.58µs) and high for the remaining locations in lines 6-310 20  Silicon Chip To understand how the memory is programmed with the pat­ terns, we first need to understand how the picture is displayed on the TV screen. Fig.4 shows the general arrangement of the blanking inter­vals and the visible screen area. The picture from our pattern generator is made up of 312 lines which are scanned horizontally, one line at a time, from top to bottom. Lines 1-23 at the top of the screen and lines 311-312 at the bottom of the screen are not seen since they are reserved for field blanking. This is the period during which the trace returns from the bottom of the screen to recommence at the top. Each line is 64µs wide, with 12µs of this period reserved for line blanking. This means that the visible area on the screen is only 52µs wide by 288 lines high. The visible picture is displayed with a 4:3 width-to-height ratio and this must be taken into account when producing the pattern coding. If this is not done, the circle will look like an ellipse, while the crosshatch and checkerboard squares will be elongated. The memory which contains the pattern codes has a capacity of 64K bytes, which is actually 65,536 bytes. Each of these memory locations is clocked at 3.2768MHz or once every 305.17578ns. If we use 210 memory locations per line, then we have 305.17578ns x 210 or 64.08µs, which is the desired line period. The 12µs line blanking interval takes up 40 memory loca­tions of the 210 total per line, leaving only 170 visible loca­tions. And with 312 lines and 210 memory locations per line, we use 65,520 locations per field which is virtually the capacity of the ROM. The 65,521th location in the memory produces a reset pulse to return the Fig.6: this oscilloscope waveform shows the line sync pulse and the colour burst signal. Note that the 10-cycle colour burst signal occurs 5.6µs after the falling edge of the sync pulse, to comply with the Australian PAL standard. The measured colour burst frequency of 4.443MHz deviates slightly from the true value of 4.433619MHz because of the small number of cycles being measured. Fig.7: these waveforms show the dot pattern (top trace) and the checkerboard pattern (bottom trace). The first dot appears di­rectly after the 12µs blanking interval. Note that the colour burst signal has been turned off here to simplify the presenta­tion of these waveforms. counters to the start of line 1. The frame rate is 305.17578ns x 65,520 = 19.555ms, which equates to 50.01Hz. Although the line and frame rates are not exactly at 64µs and 20ms, they are close enough to these figures not to cause problems. The circle is programmed into memory with its centre at memory location 125 and a horizontal radius June 1997  21 included with the crosshatch pattern. Fig.5 shows the programming codes for the various patterns which are programmed in via data lines D0-D7 for each line from 1-312. These are presented graphically so that it can be seen how each pattern is made. D7 is the sync signal and this is low for 15 locations (4.58µs) and high for the remaining locations in lines 6-310. The signal is continuously low for lines 311-5. The remaining data lines (D6-D0) are for the patterns and these also incorpo­ rate the line and field blanking intervals. As shown, all lines are high during the first 40 locations for line blanking and for lines 311-23 for field blanking. Understanding the patterns Virtually all the parts are mounted on a single PC board so that construction is really easy. The full construction details are in next month’s issue. of 50 locations. This means that the circle crosses the horizontal centre line (line 167) at memory locations 175 (125 + 50) and 75 (125 - 50). Similarly, the circle has a vertical radius of 114 lines. This means that it crosses the vertical centre line at the 125th memory location at lines 53 (167 - 114) and 281 (167 + 114). The remaining points of the circle were calculated using standard trigonometry and the circle coding Some of the patterns are relatively simple, while the others are more complicated. The easiest to understand is the raster which has all lines low for memory locations 41-210. The crosshatch pattern is more complicated. In this case, lines 30, 57, 85 (ie, every 27th line) and so on are always low from memory location 41 onwards, so that we get 10 white horizon­tal lines across the screen. For each remaining line from 24-310, the signal goes low at memory locations 41, 53, 65 and so on (ie, at every 12th memory location) to generate the vertical lines. The dot pattern works in a similar fashion, except in this case all lines are high except for lines 30, 57,85, etc which go low at memory locations 41, 53, 65 and so on to generate the white dots at these locations. The checkerboard coding is quite different, with successive blocks of 24 memory locations programmed high and low for six different groups of lines. The colour bar and greyscale pattern is derived from data lines D4, D5 & D6. Note that the bars are slightly wider at the two outside edges than in the centre of the screen (34 memory locations versus 20 for the others – see D4). This has been done to compensate for the small degree of over­scanning present in all TV sets. Next month Fig.8: the top trace here is the greyscale waveform and this shows the familiar staircase from full white to black in eight steps. The lower trace is the colour bar waveform. Note that the colour burst signals appear to be at a low frequency due to aliasing in the digital sampling process of the scope. 22  Silicon Chip That’s all we have space for this month. Next month, we will give the full circuit and construction details and describe the test procedure. SC