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The JTAGMaster: Boundary Scan Tester & In-System Programmer By Mauro Grassi 44  Silicon Chip www.siliconchip.com.au siliconchip.com.au The JTAGMaster is a boundary scan interface controller for your PC with ports for all IC manufacturers including Altera and Xilinx. As well as for in-circuit programming of FPGAs, CPLDs and selected microcontrollers, you can use it for training purposes and to create test flows for production PC boards. It will provide you with a thorough introduction to boundary scan technology. J TAG stands for “Joint Test Action Group”, a group of engineers from various companies like IBM, Texas Instruments and Philips that developed boundary scan technology. It was originally called JETAG, where the E stood for European but that was dropped when it became misleading. The group’s task was to develop a system for automated testing of PC boards given that it was becoming more costly and difficult using traditional test methods. There is an estimated ten-fold increase in the cost of repair as you move from component level faults to module level to board level and so on. For many electronic manufacturers, this economic cost was unacceptable and it became important to develop a more feasible method of testing PC boards. The result was boundary scan technology. Theory of Boundary Scan Boundary scan technology was developed in the 1980s and 1990s as a way of overcoming major problems with traditional test methods that were compounded by advances in SMT (Surface Mount Technology) and PC board making (especially multi-layer boards). In fact, it only became an IEEE standard in 1991 and is now known as IEEE 1149.1: “Standard Test Access Port and Boundary-Scan Architecture”. The traditional method of testing at the time involved a bed of nails fixture. This was literally a matrix of nails on which the device under test (DUT) was placed. Connections to test points on the DUT were made via these nails that then allowed testing to be performed. The kind of defects which one could test for using a bed of nails Fig.1: the basic structure of a single boundary scan cell. Each digital pin of a JTAG compliant device has an associated boundary scan cell (except power supply pins). This diagram shows the structure of the cell, which is logically equivalent but not necessarily illustrative of the implementation in silicon. siliconchip.com.au fixture included shorts between adjacent tracks, open circuits, component orientation, dry solder joints and others. As SMT progressed, device packages began to have many more pins than before and came in smaller and more physically constrained packages that made traditional testing near impossible. Severe limitations were imposed by such SMD packages as BGA (Ball Grid Array) where the connections to the PC board are made using small balls of solder on the underside of the IC package. Since these connections were not physically accessible on the PC board, it was impossible to perform a traditional bed of nails test on boards that contained BGA and other high density SMDs. The standard way to test BGA components before boundary scan technology was using X-rays and visual inspections that were neither cheap nor effective. At the expense of four or five extra pins on an IC’s package, boundary scan technology overcomes the limitations imposed by having to have a mechanical connection to a test point on the PC board, allowing a test instrument to directly drive pins on the periphery of a JTAG compliant IC. Under boundary scan technology, the traditional bed of nails fixture is moved inside the silicon chip and becomes Fig.2: the TAP controller finite state machine diagram. The 16 states correspond to the boxes while there are exactly two transitions leading out of every state. One is labelled 0 (low) and the other is labelled 1 (high) corresponding to the two possible states of the TMS line. The transitions occur on a low to high transition on the TCK line. August 2009  45 (Complex Programmable Logic Devices), microcontrollers and for in-circuit emulation (ICE). Boundary Scan basics Fig.3: a representation of the JTAG boundary scan architecture, including the TAP controller and the chain of boundary scan cells. Notice that the standard specifies a minimum number of data registers and instructions but manufacturers can add proprietary instructions. As a result any internal register of the IC can end up between the TDI and TDO lines. a virtual bed of nails. Boundary scan technology has itself progressed to the point where today it is used not just for testing the connectivity of PC boards but also for programming and debugging FPGAs (Field Programmable Gate Arrays), CPLDs Each pin on an IC accessible by JTAG testing has an associated circuit, called a boundary scan cell. The logically equivalent circuit for each boundary scan cell is shown in Fig.1. Note that this kind of testing is only possible on ‘digital’ devices where there are only two signal states. For analog devices, similar schemes exist equivalent to JTAG in the limited, digital case, for example IEEE 1149.4. Such mixed signal schemes are substantially more complex than the digital case. Each boundary scan cell can behave in one of four modescapture, shift, update, or transparent. In transparent mode, the parallel input is seen at the parallel output, effectively shorting out the boundary-scan cell logic. This is the normal mode for a functioning IC when it’s performing its role in a wider circuit. The other three modes pertain to JTAG debugging and have the following functions. In update mode, the content of the update flip-flop is passed on to the parallel output. In shift mode, the serial input is shifted onto the serial output, while finally in capture mode, the parallel input is transferred to the capture flip-flop. Boundary Scan signals There are four mandatory JTAG signals and one is optional. The four mandatory signals are named TDI, TDO, TCK, and TMS. They have the following functions: TI: serial data in Shown here is the JTAGMaster kit and training PC board with interface cables and instructions. Not seen here is the AIM software CD. 46  Silicon Chip siliconchip.com.au At left is the JTAGMaster hardware. The two connectors are here configured for Xilinx and Altera hardware (connectors for other manufacturers are also available). Below is the training PC board incorporating four JTAG devices. The training board can be connected to the JTAGMaster to run more pre-loaded tests using the supplied AIM software. It’s included for training purposes. TO: serial data out TCK: serial clock TMS: control signal The optional TRST is a reset signal and is active low, if it exists. A number of JTAG compliant devices can be linked together on a PC board by connecting the TI line of one device with the TO line of another. The TCK and TMS lines are connected in parallel for all JTAG devices on a PC board. Thus linked, the JTAG compliant devices on a PC board become a scan chain. The TMS line is used to control the state of the TAP controller within each JTAG device. The TAP Controller The TAP (Test Access Port) controller is a sixteen state finite state machine controlled by two digital lines, TCK and TMS. Each state has two transitions, one for when TMS is low and one for when TMS is high. The transition occurs on a low to high transition of the TCK signal. From any state, with TMS high for five consecutive clock cycles, the TAP controller ends up in its reset state. From there, you can end up in any of the other 15 states by judiciously selecting a combination of states for the TMS line, while clocking the TCK line. The TAP controller finite state machine is shown in Fig.2. There are two distinct sequences of instructions, a Fig.5: the result of reading the boundary scan cells of the Xilinx CPLD on the JTAG Master training board. The red pins indicate a high level- in this case the Xilinx CPLD has been erased. The grey pins are those for which there is no information and these are usually power supply pins which do not have associated boundary scan cells. siliconchip.com.au SHIFT-UPDATE sequence for the instruction register, and a SHIFT-UPDATE sequence for the data register (which can be one of many registers). The BYPASS instruction, for example, places the bypass register between the TDI and TDO lines in the boundary scan chain. Doing so effectively shortens the chain by omitting the bypassed device. The Instruction Register Part of the IEEE1149.1 standard is a collection of registers, only one of which is ever connected between TDI and TDO, the serial input and output data lines respectively, as shown in the architecture diagram of Fig.3. There is an instruction register, and among data registers, there is the Boundary Scan Register (BSR), a 1-bit Bypass Register and a 32-bit identification register. The latter can be Fig.6: the result of capturing the state of the Atmel microcontroller pins using the AIM software connected to the JTAG Master. The green pins are logic low while the red are logic high. The grey pins are those for which there is no information – these are usually power supply pins. Also indicated is whether the pin is a digital input or an output. August 2009  47 used for identification, being unique to each JTAG device. The Bypass register is used to shorten the scan chain, as mentioned previously, and the boundary scan register is used to perform the actual testing of the PC board on which the JTAG device sits. in the centre and not in the periphery, near the boundary scan cell logic. You can also program and verify microcontrollers, FPGAs and CPLDs using manufacturer provided standard files. The JTAGMaster is controlled using the supplied PC software. External and internal tests Using the PC software One mandatory instruction is the external test, where the test path is between two different JTAG devices. In an external test instruction, the boundary scan cells have permission to write to their outputs. The result is then captured at the other end and shifted out of the cells serially. The great thing about external testing is that passive components in the interconnect path can also be tested. Such testing of non-boundary scan devices is common using boundary scan technology. Such an external test assesses the integrity of the entire connection path between the two pins, starting and ending with the path inside the two ICs between silicon and pad. An internal test, on the other hand, tests the integrity of the signal between two pins of the same IC. The JTAGMaster is supplied with the “ABI Interface Manager” (AIM) software suite. This allows you to create your own test flows and then run them. Each test is stored in a test flow file. This makes it easy for an operator to complete the testing, as there is a step-by-step sequence. Pictures and text can be incorporated into the test flow to provide visual guidance to the test operator or for training purposes. The entire scan chain is represented graphically by a block diagram that can be edited and augmented with devices from an extensive manufacturer library. The test operator follows the test flow to complete the test, with possibly multiple pass/fail responses of the testing. A pass result for the entire test is then equivalent to a pass response for every step of the test flow. There is even a JTAG Master training PC board that has been specifically designed for training purposes. You can connect the JTAG Master to it and perform a sequence of tests using the AIM software. The training board comes with four JTAG devices, including an Atmel microcontroller, a Xilinx CPLD and an Altera FPGA. The JTAGMaster hardware The JTAGMaster consists of two dual in line header ports (one is compatible with Xilinx, while the other is compatible with Altera hardware), a column of four LEDS, one green (PASS), one red (FAIL), and two yellow (POWER and TESTING) and a USB port for connection to a computer. The device fits inside the palm of your hand. As you can imagine, every test ends with either the green or the red LED being lit to indicate respectively a pass or a fail response to the test. The JTAGMaster can be used to diagnose complex PC boards with multiple JTAG compliant devices. The pins of each JTAG device in the scan chain can be monitored for their logic level. External and internal tests on tracks and joints on the PC board can be performed easily and repeatedly. These may uncover manufacturing defects, incorrect logic levels at pins indicating a bad solder joint, a faulty device or other causes. Note that it is very rare for an IC to show signs of damage Fig.7: a test in progress. The yellow box is labelled ‘Busy’ while the test is being performed using the JTAG Master. The chosen file is an erase sequence ‘erase.jam’ for the Xilinx CPLD on the JTAG Master training board. The JTAG serial clock frequency has been selected to be 1MHz although the JTAG Master can operate at higher rates than that. 48  Silicon Chip Conclusion We found the AIM software intuitive and easy to use. Performing tests is simple, in any one of a number of industry standard file formats supplied by device manufacturers and the test flows with integrated text and pictures are a nice feature. The JTAGMaster consists of the JTAGMaster hardware, 10-way interface cable, 14-way interface cable, USB cable and AIM software on CD. The cost is $AU5800.00 plus GST. The JTAGMaster Training board, which costs $AU920.00 plus GST, also includes a USB cable. For further information, contact TekMark Australia, Suite 302, 18 Orion Rd, Lane Cove NSW 2066. Phone 1300 811 355 or visit www.tekmark.net.au SC Fig.8: the result of the test is a Pass, indicated by a green box. The green LED on the JTAG Master will also light to indicate a pass response. The selected test was actually an erase sequence for the Xilinx CPLD in the form of the file ‘erase.jam’. These are files in an industry standard format that the AIM software understands. siliconchip.com.au