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By NICHOLAS VINEN A High-Quality Digital Audio Signal Generator; Pt.1 This Digital Audio Signal Generator has TOSLINK and coax (S/PDIF) digital outputs, as well as two analog audio outputs. If a digital output is used, the harmonic distortion from a high quality DAC is extremely low. Alternatively, if you use the analog outputs the harmonic distortion of the sinewave signal is typically still very low at less than .06%. 58  Silicon Chip siliconchip.com.au CRYSTAL OSCILLATOR L DIFFERENTIAL AMPLIFIERS & FILTERS CLOCK DIVIDERS R ANALOG OUTPUTS BATTERY S/PDIF OUTPUT IC4 dsPIC33FJ64GP802 MICROCONTROLLER POWER SUPPLY TOSLINK OUTPUT PLUGPACK LCD SWITCH-MODE POWER SUPPLY CONTROL PANEL CONTROL BUTTONS A S WELL AS SINEWAVE outputs with low distortion, this Digital Audio Signal Generator produces a range of other waveforms which you would normally obtain from a highquality function generator. These waveforms include square, triangle and sawtooth etc, as well as advanced functions that include waveform mixing, pulse and sweep modes. If you connect the SPDIF digital out­put to our high-quality Stereo Digitalto-Analog Converter (DAC), (SILICON CHIP, September-November 2009), you get a sinewave output with very low distortion in the audio band. We measured around 0.0006% THD+N (20Hz-22kHz bandwidth) for a 1kHz full-scale sinewave with a sampling rate of 48kHz and less than 0.001% THD+N for any frequency between 20Hz and 2kHz. The distortion is less than 0.006% up to 20kHz (or 0.005% with a sampling rate of 96kHz). That is lower distortion than from any commercial audio generator that we know of. There is one important proviso. Using a DAC for signal generation means that there will be high-frequency switching noise in the output. This is true whether you use an external DAC or the internal one which drives the analog outputs. Usually, this will not be an issue, however it is important to keep it in mind. If you use the signal as part of a noise or distortion test, the measursiliconchip.com.au LCD Fig.1: this block diagram shows the main circuit functions of the Digital Audio Signal Generator. It’s based on a dsPIC33FJ64GP802 microcontroller (IC4) and features both analog and digital outputs. S/PDIF Audio Generator: Main Features • • Five waveform types supported: sine, square, triangle and two sawtooth • Five waveform generation modes and four output modes (see Tables 1 & 2) • • • Runs off a plugpack (9-10V DC) or a battery (4 × AA or AAA cells). • • Sweep can be manually triggered or paused/resumed/restarted • • • Can enable pre-emphasis bit on digital output if desired Frequency range: 1Hz - 24kHz in 1Hz steps at 48kHz sampling rate or 1Hz - 48kHz at 96kHz sampling rate (see text) Built-in battery voltage monitor with settable low battery voltage warning Status display for pulse and sweep modes, to show amplitude and frequency Digital output can be switched between “consumer” (S/PDIF, 20-bit data) and “professional” (AES/EBU, 24-bit data) modes 10 setting banks for storing modes and configuration Digital LCD contrast and backlight brightness control ing equipment will need to be able to ignore residuals above 20kHz. Features Five waveform types are supported: sine, square, triangle and sawtooth up/ down. Both analog channels always produce the same waveform, although the frequencies and amplitudes are independently adjustable. In certain modes, frequency or amplitude are fixed between the two channels but they can always be individually muted. The available frequency range is 1Hz - 24kHz in 1Hz steps at the default sampling rate of 48kHz. You can increase the sampling rate to 96kHz and the upper frequency limit is then 48kHz. If you set the sampling rate to the third option, 44.1kHz, the upper frequency limit is 22.05kHz. These are the Nyquist frequencies – the highest frequency that can be digitally represented at that sampling rate. Frequency accuracy and stability is limited by the crystals, so it should generally be within 50 parts per milMarch 2010  59 D1 A K PLUGPACK CON1 + 1 – 2 A OUT IN POWER SWITCH D3 REG1 7805 GND K REG2 LM3940IT-3.3 1k +3.3V OUT IN CON3 GND 10 F 10 F 47 F +3.3V 200 +5V D2 A BATTERY CON2 + 1 – 2 K L1 100 H 1 10  1W D4 A K +5V Q1 BC327 E 47k B B 100 F C C E C Q3 BC549 180 1 K Q2 BC549 ZD1 5.1V 6 7 8 Vcc Ips DrC 33k SwC A 100 F B E 150pF 560 3 Ct IC1 MC34063 Cin- 1 100 F 5 +1.25V SwE 2 GND 4 11k 33k +3.3V 100nF IC2: 74HC04 IC3: 74HC393 10M IC2c IC2a 5 100nF 11k 6 1 2 X2 11.2896MHz 3 620 68pF 33pF X1 24.576MHz 14 IC2b 4 1 O3 CP IC3a 2 MR O2 O1 O0 6 13 5 4 3 O3 CP IC3b 12 MR O2 O1 O0 8 9 10 33pF 33pF 11 7 CON4 6 8 +5V 10 15 13 TO LCD & SWITCHES 11 9 7 5 3 14 16 2 1 4 12 100nF SC 2010 1.5k S/PDIF & TOSLINK DIGITAL AUDIO SIGNAL GENERATOR 60  Silicon Chip siliconchip.com.au +5V +3.3V 150pF 10 10k 1 MCLR 100nF 13k 100nF 28 13 100nF AVdd Vdd 10k 8 2 10k 3 10 F 1 IC5a 13k DAC1LN DAC1LP DAC1RN DAC1RP 10k 26 25 15nF 150pF 23 13k 10k 6 10k 5 10 F 7 IC5b CON6 100 4 13k RB2 5 9 10k RB1 +3.3V 100nF 9 CLKO 14 CLKI 12 18 21 22 C 220 150 Q5 BC337 +3.3V CON8 RA1 16 B S/PDIF OUT IC2f E 7 RB3/ RP3 17 100k CON7 390 IC2e 13 4 150nF 10 11 10 F RB0 8 IC2d Vcap/ 20 Vddcore 11 RB4/ RP4 15 15nF 10 F 7 12 RIGHT ANALOG OUT 6 IC4 dsPIC33FJ64GP802 10 LEFT ANALOG OUT IC5: LMC6482 10 F 24 CON5 100 3 100k B C 2 100nF Q6 BC549 3 TOSLINK OUT E RA4 1 RB6 RB7 RA0 2 100k B RB8 C Q7 BC549 E RB9 RB10 RB11 Vss 8 Vss 19 RB5 14 1k B AVss 27 C Q4 BC337 E D1–D4: 1N5819 A K BC327, BC337, BC549 ZD1 A B K E REG1, REG2 GND IN C GND OUT Fig.2: the circuit diagram for the main PC board. REG1, REG2 & IC1 are the main power supply components, while IC2 & IC3 generate the clock signals. IC4 performs the signal generation and also interfaces to the LCD board. Pins 23-26 drive op amps IC5a & IC5b to produce the analog signals, while pin 6 drives the TOSLINK & S/PDIF outputs. siliconchip.com.au March 2010  61 Table 1: Waveform Generation Modes Mode Pulsed Features Single frequency, adjustable phase difference between the left & right channels Different frequencies can be output on the left and right channels Mixes signals of two different frequencies & amplitudes, output on both channels Amplitude alternates between two values with configurable on/off delays Sweep Frequency varies over time, ramping up or down over a specified time period Locked Independent Mixed Table 2: Output Modes Sampling Rate Outputs Enabled Comment 44.1kHz Digital (S/PDIF) only CD quality 48.0kHz Digital (S/PDIF) and Analog DVD quality 96.0kHz Digital (S/PDIF) only DVD-audio, etc 96.0kHz Analog only Highest quality analog lions (ppm) or 0.005% at 25°C – a typical crystal frequency tolerance. Over a wider range of temperatures, the drift might be up to 100 ppm (0.01%). This translates to an actual 1kHz frequency of between 999.9Hz and 1000.1Hz. We measured 999.95Hz from our prototype. The output amplitude ranges from 0dB to -98dB in 1dB steps, as well as an “off” setting in place of -99dB. Amplitude accuracy is good, with a -90dB 1kHz sinewave actually being measured as -89.37dB using our Audio Precision System One. If you use the analog outputs, the 0dB amplitude level is close to 1V RMS. Alternatively if you use the recommended external DAC, 0dB translates to around 2V RMS, with much lower distortion. Waveform generation modes There are five main waveform generation modes to choose from (see Table 1) and four output modes (see Table 2). Taken together, the waveform type, waveform generation and output modes make for a total of 100 different mode combinations. Any generation mode can be combined with any waveform type, although you can’t have different waveform types on each channel. Table 4 gives specific information on each waveform generation mode. Circuit details The general details of the unit are shown in the block diagram of Fig.1. As is usual with a project of this complexity, it is based on a high performance microcontroller, IC4. This generates the digital and analog output signals, in response to commands from the control panel pushbuttons. It also drives the LCD panel. Note that there are two digital outputs: TOSLINK and S/PDIF coaxial. Applications • • • • • RMS and music power testing for power amplifiers • • • Analog circuit prototyping and development Speaker placement optimisation Sub-woofer or speaker crossover optimisation Finding faults in audio equipment Audio quality testing for analog or digital audio equipment with appropriate measurement equipment (THD, SNR, channel separation, intermodulation distortion, frequency response, etc) Testing DACs or other equipment that accept a digital audio signal Whenever you need an adjustable audio-frequency signal source. 62  Silicon Chip Turning to the full circuit in Fig.2, IC4 can be seen to be a dsPIC33FJ64GP802 16-bit Digital Signal Controller. This microcontroller runs at up to 40MHz and has 64KB of flash program/data memory and 16KB of Random Access Memory (RAM). Because it’s a 16-bit processor, it can manipulate much larger numbers than an 8-bit microcontroller, improving its efficiency in dealing with audio data. Its Data Converter Interface (DCI), internal Digital-to-Analog Converter (DAC) and Direct Memory Access (DMA) support are all especially useful for this project. The dsPIC33 runs off 3.3V which is provided by an LM3940IT-3.3 low drop-out linear regulator (REG2). This ensures that the microcontroller can run with cells developing as little as 0.9V each (3.6V total), by which time most of the energy has been extracted from them. You shouldn’t drain NiMH cells this low but it’s OK with alkaline or dry cells. The rest of the power supply is a little more involved. We need 5V for the LCD and its backlight. Because the battery voltage could be above 5V (with NiMH cells being charged or fresh primary cells) or below 5V (NiMH cells being discharged or flat primary cells), the LCD supply needs to be able to increase or decrease its input voltage. We deliberately kept it simple by combining a discrete low drop-out linear regulator with a switchmode boost regulator. This keeps size and cost down and uses readily available parts while retaining reasonable efficiency. The discrete linear regulator consists of three transistors (Q1-Q3), zener diode ZD1 and two resistors. While it does not have particularly good load regulation its dropout is very low (around 0.1V) which means that when the battery voltage is below 5V it doesn’t waste much power. It is followed by the boost regulator which is built around IC1, an MC34063 switchmode DC-DC converter. It switches power through the inductor at around 100kHz, keeping the output at 5V. This ensures that the LCD continues running as long as the microcontroller does. It also keeps the LCD backlight brightness and contrast constant as the cells discharge. The 7805 regulator (REG1) is mainly there to protect the LM3940IT-3.3 from voltages above its maximum rating siliconchip.com.au CON9 (+5V) 10 8 2 6 Vdd 15 4 13 5 11 6 15 ABL RS 100nF 16x2 LCD MODULE R/W EN CONTRAST 3 4 D4 D5 D6 D7 11 12 13 14 GND D3 D2 D1 D0 1 10 9 8 7 KBL 16 9 7 5.6 5 3 S6 S3 S2 S7 S5 S1 S2 S3 S4 S5 S6 S7 S4 S1 12 A 2 A D7 D10 K A K A K A D9 D11 D6 K A K A D8 D5 K = = = = = = = LEFT MUTE UP RIGHT MUTE LEFT SELECT RIGHT DOWN K 1 14 16 D5–D11: 1N4148 SC 2010 S/PDIF & TOSLINK DIGITAL AUDIO SIGNAL GENERATOR A CONTROL BOARD K Fig.3: the control board circuit. It consists of a 16x2 LCD module plus pushbutton switches S1-S7 and isolating diodes D5-D11. The microcontroller (IC4) on the main board reads the switch states and updates the display. (7.5V). The 1kΩ & 200Ω resistors associated with REG1 are used to increase its output to around 6.8V, ensuring that it always exceeds the battery voltage. That way, the battery can’t be drained when the plugpack is connected and it also allows rechargeable cells to be kept charged reasonably well. Clock generators There are two oscillators to produce the three sampling clocks. One runs at 11.2896MHz (44.1kHz × 256), while the other runs at 24.576MHz (96kHz × 256). The 48kHz rate is generated within the microcontroller by halving the 96kHz clock. While the 11.2896MHz crystal has its own oscillator circuit (driven by IC2a, one section of a 74HC04 hex inverter), the 24.576MHz crystal uses the dsPIC33’s internal oscillator amplifier. It has a dual purpose – to generate the clock for 96kHz sampling and also to provide the dsPIC’s system clock. Fortunately, it’s easy to configure the dsPIC’s internal PLL to derive 39.936MHz from the 24.576MHz crystal, which is close enough to its 40MHz operating limit. As a result, the siliconchip.com.au microcontroller is able to shut down the 24.576MHz oscillator if the battery is flat to save some power. The 74HC393 ripple counter, IC3, has two purposes. First, it divides the oscillator frequencies to the S/PDIF encoding clock frequency we need, 5.6448MHz & 12.288MHz, which is 128 times the sampling rate in each case. Second, it ensures that the clocks have a 50% duty cycle. Digital outputs The digital audio signal is fed to both TOSLINK (optical) and coaxial outputs. For the optical output, the signal from the microcontroller’s Data Converter Interface (DCI) is sent directly to the TOSLINK transmitter (CON8). For coaxial, we use three inverters from IC2, connecting them in parallel to buffer the signal which is then coupled via the 150nF capacitor and fed to a resistive divider to produce the correct voltage and impedance levels for S/PDIF signals. Analog outputs The dsPIC’s internal DAC is a DeltaSigma type. It’s much like the SILICON CHIP Stereo DAC but has inferior audio quality. Its residual switching noise is fairly high and is at 12.288MHz or 24.576MHz, depending upon the sampling rate. The dsPIC33 actually has four DAC Table 3: Performance Measurement <at> 1kHz, SR = 48kHz, BW = 20Hz-20kHz Internal DAC External DAC THD+N 0.06% 0.0006% Signal-to-Noise Ratio -66dB -111dB Channel Separation -66dB -107dB Attenuation at 20Hz -0.07dB -0.013dB Attenuation at 20kHz -0.67dB -0.177dB Attenuation at 40kHz (SR = 96kHz) -1.6dB -2.4dB March 2010  63 This is the view inside the prototype using the Jaycar case. The main board mounts in the base, while the control board is installed on the lid and the two connected via a ribbon cable & IDC connectors. The full construction details will be in Pt.2 next month. The photo below right shows the digital and analog outputs at the top of the case. output pins, ie, differential outputs for the left and right channels. As recommended in the dsPIC33 data sheet, a pair of op amps is used to make the conversion from differential to singleended outputs. In fact, we have used an LMC6482, a dual CMOS rail-to-rail amplifier (IC5), for this task to get the best signal quality from the limited supply rail of only 5V. In order to remove most of the highfrequency switching noise, we have added two filter stages to the differential amplifier stages of IC5. The first is the active filter in the op amp feedback networks, comprising the 150pF capacitors and 13kΩ resistors. The second filter involves the passive filters (100Ω and 15nF capacitor) after the 10µF output capacitors and just before the output connectors (two RCA sockets). Control panel All the components mentioned thus far are mounted on the main PC board. It is connected to the control panel PC board via CON3, shown at the lefthand side of Fig.2. The circuit of the control board is 64  Silicon Chip shown in Fig.3. It accommodates the LCD module and seven pushbutton switches. The two boards are connect­ ed via a 16-wire ribbon cable with IDC headers, ie, from CON3 on Fig.2 to CON9 on Fig.3. The LCD’s backlight brightness and contrast are regulated by the microcontroller. The brightness is adjusted via an NPN transistor (Q4) which is pulsewidth modulated at 50kHz; increasing the duty cycle increases the brightness. This not only allows you to adjust it as desired (via the relevant pushbutton) but also saves battery usage because only a low-value (5.6Ω) current limiting resistor is required. The default 25% duty cycle allows the LCD to be viewed under virtually any lighting condition without being too much of a drain on the battery. The contrast control is a little more tricky, since we need a variable current sink to adjust it properly. This too is achieved via a 50kHz PWM signal from pin 4 of IC4 to the base of NPN transistor Q5 which pulls current from the LCD display through a 1.5kΩ resistor. If the resistor is switched on by Q5 for, say, 50% of the time, this makes the circuit roughly equivalent to a 3.0kΩ resistor. A 100nF MKT capacitor filters this switching to provide a variable supply to the LCD between its VCC and VO pins. Button multiplexing While 28 pins on a microcontroller may seem like a lot, in reality it was difficult to wire up everything needed for this project. Of the 28 pins, nine are dedicated to power supply, the main oscillator or reset functions, leaving 17 general-purpose pins. After subtracting the signal generator and battery monitoring functions, we’re left with only nine for both LCD communications and button sensing for the user interface. Communicating with the LCD without additional components requires at least seven pins, four for data I/O and siliconchip.com.au Parts List 1 IP67 polycarbonate enclosure with transparent lid, 171 × 121 × 55mm (Jaycar HB-6218) or 186 x 146 x 75mm (Altronics H-0330) 2 16-pin IDC crimp connectors 1 4AA side-by-side battery holder with leads (or 2 × 2AA side-byside battery holders) 1 SPST rocker switch (Jaycar SK0960, Altronics S3188) or miniature/sub-miniature toggle switch 2 4.8mm female spade crimp connectors (only if SK0960/ S3188 switch or similar is used) 1 2.1mm bulkhead male DC power connector (Jaycar PS0522, Altronics P-0622) 1 300mm length of 16-way ribbon cable 1 300mm length of double-sided tape 1 300mm length of red medium duty hook-up wire 1 300mm length of black medium duty hook-up wire Optional: 4 x low self-discharge AA 2000mAh NiMH cells (Jaycar SB1750, Altronics S4705 × 2) Optional: 9V 500mA DC regulated plugpack or 7.5V 500mA DC unregulated plugpack, with 2.1mm ID plug (nominal output 9.5V <at> 250mA, acceptable range 9-11V) Main Board 1 PCB, code 04203101 (Jaycar version) or 04203103 (Altronics version), 109 × 102mm 1 100µH bobbin inductor with 2.54mm pin spacing (Jaycar LF-1102) or 1 x 100µH axial inductor (Altronics L7034) 1 PC-mount RCA connector (black) 1 PC-mount RCA connector (white) three for control. Fortunately, there is a way to connect the seven buttons using the two remaining pins, by timemultiplexing the LCD I/O lines. When there is no communication siliconchip.com.au 1 PC-mount RCA connector (red) 1 16-pin IDC socket 3 2-pin polarised headers 3 2-pin polarised header connectors 1 2-pin shorting block 6 M3 x 6mm machine screws (or 2 if Altronics H-0330 box is used) 2 M3 nuts 2 M3 flat washers 2 M3 star washers 1 PC-mount TOSLINK transmitter (Jaycar ZL-3000, Altronics Z-1601) 1 28-pin narrow machine-tooled IC socket 2 14-pin machine-tooled IC sockets 2 8-pin machine-tooled IC sockets Semiconductors 1 MC34063 switchmode DC-DC converter (IC1) 1 74HC04 hex inverter (IC2) 1 74HC393 dual 4-stage ripple counter (IC3) 1 Microchip dsPIC33FJ64GP802 microcontroller programmed with 0420310C.hex (IC4) 1 LMC6482 dual op amp (IC5) 1 BC327 transistor (Q1) 2 BC337 transistors (Q4,Q5) 4 BC549 transistors (Q2,Q3, Q6,Q7) 1 LM7805T 5V regulator (REG1) 1 LM3940IT-3.3 or TS2940CZ-3.3 3.3V regulator (REG2) 4 1N5819 Schottky diodes (D1-D4) 1 5.1V 1W zener diode (ZD1) Crystals 1 24.576MHz crystal (HC-49, low profile if possible) 1 11.2896MHz crystal (HC-49, low profile if possible) Capacitors 3 100µF 16V electrolytic 1 47µF 16V electrolytic 6 10µF 16V electrolytic occurring with the LCD, its I/O lines are unused and are high impedance. So, we connect these four pins to one end of each of the seven buttons (six sharing three lines between them). The 1 10µF 16V tantalum 1 150nF MKT polyester or polycarbonate 8 100nF MKT polyester or polycarbonate 2 15nF MKT polyester or polycarbonate 3 150pF ceramic 1 68pF ceramic 3 33pF ceramic Resistors (0.25W, 1%) 1 10MΩ 1 390Ω 3 100kΩ 1 220Ω 1 47kΩ 1 200Ω 2 33kΩ 1 180Ω 4 13kΩ 1 150Ω 2 11kΩ 2 100Ω 7 10kΩ 1 10Ω 1 1.5kΩ 1 10Ω 1W 2 1kΩ 2 1Ω 0.6W 5% 1 620Ω 7 0Ω (or wire links) 1 560Ω Control Board 1 PCB, code 04203102, 87 x 73mm 7 1N4148 diodes (D5-D11) 1 100nF MKT polyester capacitor 1 5.6Ω resistor 1 0Ω resistor (or wire link) 1 16-character x 2-line alphanumeric LCD with backlight (Jaycar QP-5512; Altronics Z-7013) 7 tactile pushbutton switches with long actuators (Altronics S1119) 7 button caps (Altronics S-1482) 1 16-pin IDC socket 1 16-pin single row female header 1 16-pin single row male header 6 M3 x 9mm tapped Nylon spacers 4 M3 x 12mm tapped Nylon spacers 4 M3 x 6mm machine screws 4 M3 x 10mm countersunk machine screws 4 M3 x 15mm machine screws 2 M3 nuts Note: for Altronics box replace the 12mm spacers with 9mm spacers, delete the M3 nuts and add 8 x M3 star washers other side of each button is connected via 1N4148 diodes to two NPN transistors, Q6 & Q7; the diodes are on Fig.3 while the transistors are on Fig.2. When those two transistors are March 2010  65 Fig.4: this the default Locked Mode display. The unit generates a 1kHz sinewave signal with a 180° phase difference between the two channels. Fig.5: this is the default Sweep Mode display. Both channels output a sinewave which starts at 20Hz and ramps up to 20kHz over a 10s period. Fig.6: the default Pulsed Mode display. Both channels alternate between 0dB and -30dB amplitude each second (100ms high; 900ms low). Fig.7: the output/wave type setting display. In this case, the sampling rate is 48kHz and a sinewave is being generated. switched off by the microcontroller, the diodes ensure that they do not affect the LCD I/O lines, regardless of whether any of the buttons are pressed. However, we can sense the button state when those transistors are turned on (one at a time) while we simultaneously enable the pull-up resistors on the four LCD I/O lines, pins 17, 18, 21 & 21 of IC4. In this state, any button that is pressed will pull its corresponding I/O line low if its associated transistor is actively sinking current. Thus we can periodically scan the buttons without affecting the LCD. Battery charging As mentioned, Nickel Metal Hydride (NiMH) rechargeable cells can be used to power the unit and you can add a 10Ω 1W resistor to trickle charge them whenever the plugpack is connected. We’ve provided an appropriate mounting point on the PC board. The final trickle charge current for 66  Silicon Chip an NiMH cell varies somewhat but is typically between C/10 and C/40, ie 1/10th to 1/40th of its rated amp-hour capacity. We’ve set the resistor so that it provides a little under 100mA to the cells once they are fully charged, which equates to a rate of C/20 for 2000mAh cells. Keep in mind that the charge current will be appreciably higher than this when the cells are flat, as it decreases during charging. If you use cells with a lower capacity than 2000mAh then you need to increase the value of the resistor accordingly. For example, 800mAh cells would require a 27Ω 1W resistor rather than the 10Ω resistor specified. For 600mAh cells, you would use 33Ω. We don’t recommend you exceed C/20 for any NiMH cells. Trickle charging is a lot slower than removing the cells and charging them properly but it is more convenient. This is especially true if you will generally run the signal generator off mains power with occasional battery use in-between. This way, the battery will always be ready for those times you need to take it into the field or are away from a convenient power point. It also saves you the hassle of having to unscrew the lid to gain access to them. Heat dissipation in the resistor will be kept under its 1W rating as long as the battery never goes below 3.6V. It’s not a good idea to discharge NiMH cells to that extent anyway. If you do apply DC power with a battery below 3.6V, its voltage should rise rapidly and reduce the charge current to the safe range but the best option in that case would be to remove the cells and re-install them once they have been properly charged. If you install this resistor, you can only use NiMH or Nicad cells in the device. If you will ever use alkaline or dry cells, do not install it or they might overheat and leak if you accidentally plug it into DC power. • Software details With the microcontroller running at 40MHz and outputting audio data at 96kHz, we only have 40M/96k = 416 processor cycles to generate and output each data point for both channels. This may sound like plenty of cycles but there is much to do in that time. The steps set out in Table 5 must occur for each set of four samples that are output (experimentally determined to be the optimal number). Because this all has to be executed in The software development for this project was complicated by the number of modes and features and because all the modes have to run in real time up to the maximum 96kHz sampling rate. We were able to pack it all into the 64KB of flash memory – but only just. The software consists of a number of modules: • LCD display routines • Button sensing & repeat logic Interface code – determines what to display on the LCD and how to react to button presses • Digital & Analog output control • Waveform generation (sine table lookup, linear interpolation, other waveform calculations) • Output amplitude scaling • Waveform generation modes (mix­ ed, sweep, pulsed, etc) • S/PDIF encoding • Direct Memory Access (DMA) Interrupt Servicing • Communication between the interface code and the waveform generator • EEPROM emulation for storing settings in flash memory (provided by Microchip) • Battery monitoring & power saving The interface code runs in the main loop, while all the waveform generation happens asynchronously in the DMA Interrupt Service Routine (ISR). This way, the time-critical waveform generation has absolute priority. If it did not provide the output data within a certain amount of time in all cases, the waveforms would be subject to glitches. In practice, this scheme works well because even though the interface only has a small percentage of the CPU time remaining to run, it is not an intensive task so the delay is not noticeable. What ties it all together is the communication code that passes data from the interface to the ISR. It is implemented so that changes in the output are as seamless as possible. Simultaneous analog and digital output is only available at the 48kHz sampling rate. This is because at 96kHz we only have half as much time to generate the waveform data and it’s simply too slow to output both sets of data. We can’t enable the analog outputs at 44.1kHz either because the DAC clock input is less flexible than the DCI’s. Real-time processing siliconchip.com.au Table 4: Waveform Generation Mode Details Locked Mode Fig.8: this screen grab shows a 1kHz sinewave from one of the analog outputs. Options: Frequency (Hz), phase difference between channels (0-360°), left channel amplitude, right channel amplitude. Output: Each channel generates a waveform of the same type and frequency, with independent amplitudes. The phase difference between the channels is maintained at the specified number of degrees. Uses: As well as general signal generation duty, especially when you want both channels to provide identical signals (ie, set phase difference to 0°), this could be used (for example) to test the power delivery capability of a bridged stereo amplifier, by feeding the same sine waveform to its two inputs 180° out of phase. Independent Mode Options: Left channel frequency (Hz), right channel frequency (Hz), left channel amplitude, right channel amplitude. Output: Each channel generates a waveform of the same type, with independent amplitudes and frequencies. There is no fixed phase relationship between the channels, although if one frequency is an integer multiple of the other the generator will attempt to keep them in phase (eg, 1kHz & 2kHz). Uses: Could be used, for example, to measure high-frequency feed-through between channels or as two independent simple signal generators. Mixed Mode Fig.9: this is the 1kHz triangle wave output from one of the analog outputs. under 416 cycles per sample under all circumstances (in reality slightly less), it became obvious that we needed to specialise the ISR routines for certain modes. The final version of the software has 31 different ISR subroutines. Each one covers some subset of the 100 possible mode combinations. Some handle a single mode, others several. The more complex the mode combination, the more specialised the ISR must be to run fast enough. It’s a balancing act between having few enough routines to fit in flash memory but specialising them sufficiently to run fast enough. As an example of a mode-specific ISR, there is one specifically to handle a high to low frequency geometric sweep with a sinewave format at the 48kHz sampling rate. Whenever you change the mode, the code determines which handler is appropriate and installs it. Sinewave generation is the slowest of all the waveforms. Because it takes too long to calculate the sine values from first principles, we use a 6000 entry quarter-sine table stored in the flash memory. This takes up approximately 18KB of the available 64KB. siliconchip.com.au Options: Frequency A (Hz), frequency B (Hz), amplitude A, amplitude B. Output: Both channels generate the same waveform, although they can be independently muted. The output consists of the average of the two waves specified. There is no fixed phase relationship between the waves, although if one frequency is an integer multiple of the other the generator will attempt to keep them in phase. Because they are averaged, the maximum amplitude of either of the two waves is effectively half that as in the other modes. Uses: Could be used to measure intermodulation distortion with the correct analysis equipment (eg, FFT analyser) or alternatively, used when you need a repetitive waveform with some harmonics. Pulsed Mode Options: Frequency (Hz), on amplitude, off amplitude, on time (0-999ms), off time (0-9999ms). Output: Both channels generate the same signal but can be independently muted. The output consists of the specified waveform and frequency, with a varying amplitude. The scale is set to the “on amplitude” for the period of “on time”, then it changes to the “off amplitude” for the period of “off time”. This process repeats forever. Both amplitude changes occur on the first available zero crossing to prevent glitches in the output unless the frequency is so low as to make it impractical (<500Hz, lower in some modes). Uses: Primarily to measure “headroom” or “music power” of an amplifier but there are other situations where a pulsed waveform may be useful. Sweep Mode Options: Start frequency (Hz), finish frequency (Hz), sweep time (0-99.9s), off time (0-99s), amplitude. Output: Both channels generate the same signal, although they can be independently muted. The signal consists of the specified waveform and amplitude, with the frequency sweeping between the specified start and end points. If the start frequency is set lower than the finish frequency then it will sweep up, otherwise it will sweep down. By default, the sweep rate is exponential, which means that the time it takes for the frequency to double (or halve) is consistent. However, if for some reason you want the sweep to have a constant rate of frequency change (in Hz) you can enable the “linear sweep” mode. Uses: Frequency response measurements for analog equipment and speakers, speaker crossover and placement optimisation and sub-woofer matching. March 2010  67 Table 5: Real-Time Processing Steps (1) Enter ISR (2) Save register context (3) For each of the four samples: (a) Calculate the next waveform point value; (b) Scale it to the appropriate amplitude; (c) If mixing, calculate the other waveforms and average them; (d) If outputting S/PDIF, perform S/PDIF bitstream encoding; (e) If analog outputs are active, place sampling value in DAC buffer; ( f ) Update the waveform position; (g) Determine whether we are in a special mode (pulsed or sweep); (h) Adjust amplitudes/frequencies over time as necessary; ( i ) Write to DMA buffer. (4) Clear interrupt flag (5) Restore register context (6) Leave ISR Normally, tables stored in flash on a dsPIC device take up 50% greater space than you would expect because of the way it packs 16-bit data words into the 24-bit flash. However, we came up with a way to use all 24 bits of each instruction word to store the sine table data. The possibility of packed flash storage for data is mentioned in the Microchip documentation but they do not explain how to do it. In the end we had to “pretend” the sine values were instruction op-codes and use the TBLRDL and TBLRDH assembly instructions to access them. The remaining subroutines in the software are straightforward, if somewhat complex. The main loop scans to see whether any buttons are pressed and uses some logic to determine what any given button does, depending on the current screen. It then instructs the LCD to update and, if necessary, changes the waveform generation settings. All the while, the waveform generation code is running as needed to keep the DMA buffers full. S/PDIF output The S/PDIF output code is a little tricky. The S/PDIF bi-phase serial stream encodes 64 bits per sample, so for 96kHz the bit rate is 96,000 × 64 = 6.144Mbits/second. Logically, the easiest way to generate this stream is with some kind of serial output peripheral, such as SPI. However, the bi-phase (aka NRZI) encoding complicates matters. Rather than adding external biphase encoding hardware, we decided the best approach was to double the serial bit rate and do the bi-phase encoding in software. This makes the maximum bit rate 12.288MHz. For­ tunately, this is within the capabilities of the Data Conversion Interface (DCI) unit in the dsPIC33. However, the maximum clock rate it is able to generate internally is the master clock divided by four, ie, 10MHz. The solution is to generate the clock externally and use the DCI in slave mode. The 12.288MHz clock signal from the 74HC393 is fed into the DCI and this determines the rate at which data is read out of RAM via DMA and streamed to the DCI data output. In order to make the software biphase encoding fast, a 256-entry, 16-bit look-up table is used. This allows us to take eight bits of data and with a single RAM lookup and conditional bit inversion, compute the bi-phase encoded bit sequence. Then there’s the issue of the logical bitstream generation, ie, coming up with the S/PDIF data stream itself. It involves combining the audio sampling data with some status bits. We generate a table of these bits when the mode is set and feed them into the logical stream as it’s generated to save time. What’s coming That’s all for this month. Next month, we’ll show you how to build the two boards and install them in SC the case. Are Your Issues Getting Dog-Eared? Are your SILICON CHIP copies getting damaged or dog-eared just lying around in a cupboard or on a shelf? Can you quickly find a particular issue that you need to refer to? REAL VALUE AT $14.95 PLUS P & P Keep your copies of SILICON CHIP safe, secure and always available with these handy binders Available Aust, only. Price: $A14.95 plus $10 p&p per order (includes GST). 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