Fullscreen HTML5Med Res (??MB)HTML4

By NICHOLAS VINEN Digital Audio Delay . . . brings the sound and picture into perfect “lip sync” Do you have a large plasma or LCD TV set and a home-theatre system? If so, you may have problems with sound and picture synchronisation (lip-sync). This Digital Audio Delay unit allows you to get the picture and audio perfectly matched. L IP SYNC PROBLEMS can occur because modern TVs do a lot of video processing before the signal gets to the screen. Some sets (usually 100Hz or 200Hz types) can delay the picture by several hundred milliseconds. If you’re using the TV’s internal speakers, it will delay the sound by an appropriate amount so that they match but if you’re using external speakers 26  Silicon Chip for better sound quality, this won’t necessarily be the case. Synchronisation problems are usually evident if you’re connecting a DVD/Blu-ray player to the TV using a component video or composite video cable (ie, an analog connection) and feeding the sound direct to your hometheatre system. Sound sync problems can also occur with earlier HDMI systems but note that the HDMI 1.3 standard introduced automatic audio synchronisation to solve this problem. Some DVD/Blu-ray players, hometheatre amplifiers and set-top boxes also have built-in audio delays but they sometimes don’t provide a long enough delay or a fine enough adjustment to get the synchronisation just right. By contrast, this unit provides siliconchip.com.au 16-BIT SERIAL-TOPARALLEL ADDRESS LATCH (IC3, IC4) INFRA-RED REMCON INPUT (IRD1) CON2 S/PDIF INPUT 512K x 8-BIT STATIC RAM (IC2) ADDRESS DATA AMPLIFIER (IC6a/b) AUDIO DATA OUTPUT BUFFER (IC6d/e/f) DATA INPUT SELECT TOSLINK RECEIVER S1 S/PDIF DECODER (IC8, DIR9001) TOSLINK TRANSMITTER CLOCK MICROCONTROLLER (IC1) CON3 S/PDIF OUTPUT 8MHz CRYSTAL OSCILLATOR (IC5c/d) Fig.1: block diagram of the Digital Audio Delay. The incoming audio signal comes in either via coax to CON2 (and is then amplified) or is fed in via a fibre optic cable (TOSLINK). S1 selects between the two. IC8 recovers the clock signal and then the data and clock pass to microcontroller IC1. This buffers the audio in external SRAM IC2, with IC3 & IC4 used to select the storage address. The delayed audio is then simultaneously output via a TOSLINK transmitter and buffered RCA coax output (CON3). The crystal oscillator is used by IC1 to generate its instruction clock. an adjustable delay from 20-1500ms in 10ms steps. It can handle Dolby Digital (AC3), Digital Theatre System (DTS) and linear PCM audio with a sampling rate of up to 48kHz. That covers most video recording media and broadcasts. The unit can accept either an S/PDIF or TOSLINK digital audio input and because the delay is done digitally, it won’t affect sound quality. You set the delay once using a universal infrared remote control and it remembers it from then on. The delay can be temporarily “defeated” (switched off) using the remote control when it isn’t required (by pressing the mute button). It wasn’t possible for us to check it with all available multi-channel audio formats (there are quite a few) but most should work. The main restriction is the data bit rate; our design can handle up to 2.3Mbit/s. For example, we haven’t tried it with Dolby Digital Plus or DTS-ES but they should be within its capabilities (depending on the exact encoding the player uses). In reality, the upper limit is actually higher than 2.3Mbit/s but note that the unit is not fast enough to handle 96kHz linear PCM (eg, on DVD audio discs) which is over 4Mbits/s. Operating principle Digital audio from CD, DVD and Blu-ray players is transmitted using a protocol called S/PDIF, for Sony/ Philips Digital Interconnect Format. The optical version, developed by Toshiba, is called TOSLINK (see the accompanying panel for a detailed description of the S/PDIF format). This circuit is partly based on previously published audio projects, the most recent being the SportSync (May 2011). However, that project delayed an audio analog signal by using a micro to digitise it, then delaying the digitised signal and converting it back to analog audio using the micro’s internal digital-to-analog converter. However, we cannot use the same method here because we are delaying a digital audio stream – see Fig.1. The problem here is that, ideally, we need to delay the raw S/PDIF stream to preserve it in its entirety. But virtually all S/PDIF receiver ICs split the raw data into separate audio and data streams, which appear at pins 12 & 15-18 in the case of the Texas The unit can accept either an S/PDIF (coax) or TOSLINK digital audio input, with a slide switch used to select between them. The delayed signal is then fed to a hometheatre amplifier or to a stereo DAC (digitalto-analog converter) to drive a conventional hifi audio amplifier. siliconchip.com.au December 2011  27 #4672 #4673 #4670 #4671 #4669 #4667 #4668 #4665 #4666 CIRCULAR STORAGE BUFFER (4680 x 112 byte blocks) #4664 #4 #3 #1 #2 #4680 #4679 #4677 #4678 #4675 #4676 #4674 External SRAM sample blocks are 112 bytes each (16 frames x 7 bytes), 524,160 bytes total. Delay Adjustment IC2 (SRAM) 8-BIT DATA BUS, 19-BIT ADDRESS BUS CIRCULAR PLAYBACK BUFFER (8K bits raw S/PDIF data) SERIAL DATA IN RB2 CLOCK RB1 DATA CONVERTER INTERFACE (INPUT) IC1 (dsPIC MICRO) #1 #2 2 x DMA BUFFERS #3 #4 CIRCULAR RECORDING BUFFER (8K bits raw S/PDIF data) #1 #2 #3 #4 2 x DMA BUFFERS DATA CONVERTER INTERFACE (OUTPUT) SERIAL DATA OUT RB0 Local RAM buffers are 2K bits = 256 bytes each, 2K bytes total plus 586 bytes (4680 bits) to store preamble info. Fig.2: the general audio buffering arrangement. S/PDIF serial data is received by the DCI peripheral and placed into one of two DMA buffers. These are then copied into one of four local RAM buffers (the data is aligned at the same time). The main program loop then decodes the S/PDIF data and copies it into an SRAM block which is later retrieved and re-encoded into one of four output buffers. These are then copied into the outgoing DMA buffers by an interrupt handler and converted into a serial stream again by the output section of the DCI module. Instruments DIR9001 we are using here. We would need a bigger micro (inevitably a surface-mount type with more pins) in order to reconstitute the S/PDIF stream from these separate data streams. So we looked for another way. While it is not documented in the data sheet, the DIR9001’s system clock output (SCKO) signal is in phase with the incoming S/PDIF stream. This clock is generated by a voltage controlled oscillator (VCO) which is part of a phase-locked loop (PLL). So we use the system clock output to allow the micro to receive and delay the S/PDIF raw data stream. In fact, we don’t use any of the output data streams from the DIR9001. We really just use its PLL and VCO. By tying its PSCK0 and PSCK1 pins to ground, we set the system SCKO clock to 128 times the sample rate, typically 48kHz, giving a frequency of 6.144MHz. The biphase-coded S/PDIF data is clocked at this same rate so the SCKO rising edges coincide with each possible level transition in the S/PDIF data stream. As a result, the falling edges occur Specifications Supported formats: Linear PCM up to 48kHz, Dolby Digital (AC-3), DTS and similar compressed formats Input: S/PDIF coaxial or TOSLINK, selectable by rear-panel switch Outputs: S/PDIF coaxial and TOSLINK (both available simultaneously) Delay range: 20-1500ms in 10ms steps; set using a universal remote control Power supply: 9-12V DC, 150mA plugpack 28  Silicon Chip when the data is in a stable state (low or high) and with the micro set to sample the raw S/PDIF data on these edges, the resulting data is an exact replica of the incoming bits. To avoid extra complexity, we also use the clock recovered from the incoming S/PDIF data stream to clock the out­ going delayed data. Having received the audio data, the micro feeds it into a static RAM buffer for a set period before it is retrieved and output. To delay the raw data stream by one second we would need 6.144MHz x 1s = 6.144Mbit of storage. But we’d rather use a 4Mbit (512KB) SRAM chip since these are cheaper than 8Mbit SRAMs and are available in easier-to-solder packages (and require one less address line). Our solution is to decode the biphase mark coding (BMC) and store the decoded data in RAM. It can then be re-encoded after being read back and before transmission. This more than doubles the amount siliconchip.com.au of data that can be stored in the buffer; each 128-bit S/PDIF frame decodes to 56 bits of data (we discard the preambles and re-insert them later) for an increase in memory usage efficiency of 129%. With this method, a 512KB SRAM fits over 1.5 seconds worth of data at the typical rate (6.144MHz). The encoding and decoding can be done with RAM table lookups and since the micro saves a lot of time storing and retrieving less data, overall this method is faster too. The SRAM is used as a circular buffer – see Fig.2. Decoded data is constantly being written to it, starting at the lowest address and working its way upwards and then wrapping around once it reaches the top. Playback occurs from a different position in the buffer and proceeds in a similar manner. The difference between the recording and playback addresses determines the delay. Since the number of frames and thus the number of bits to delay depends on both the delay time set and the incoming data rate, the difference between the addresses is computed based on the rate at which incoming buffers are being filled. When this rate changes, this is automatically re-calculated. The micro’s 8MHz clock (from an external crystal oscillator circuit) is used as the reference frequency, to calculate the absolute time between buffers. The delay time is set by remote control and is stored in flash memory so that it doesn’t have to be reset each time. The delay can be temporarily cancelled or re-instated with a single button press on the remote control. Operation details Referring again to the block diagram (Fig.1), for S/PDIF over coax, the signal goes to CON2 and is amplified to 3.3V peak-to-peak. It then passes through switch S1 to microcontroller IC1 and also to S/PDIF decoder IC8 for clock recovery (ie, SCKO). With S1 in the other position, the TOSLINK input (RX1) is selected instead. Microcontroller IC1 stores the in­ coming data in 512KB SRAM IC2, using two 8-bit latches (IC3 & IC4) to select the appropriate storage address. The unit is controlled via infrared receiver IRD1. This sends the raw RC5 protocol data to microcontroller IC1 which decodes it. After having spent an appropriate siliconchip.com.au Parts List 1 PCB, code 01212111, 103 x 118mm 1 low profile instrument case, 140 x 110 x 35mm (Jaycar HB5970, Altronics H0472) 1 universal remote control (eg, Altronics A1012 or Jaycar AR1729) 1 front panel PCB, code 01212112, 108 x 30mm 1 rear panel PCB, code 01212113, 108 x 30mm 2 100µH axial inductors (L1 & L2) 1 8MHz HC-49 crystal (X1) 1 PCB-mount DC socket (CON1) 1 PCB-mount right-angle slide switch (S1) (Altronics S2070) 2 switched RCA sockets, black (CON2, CON3) 1 3-pin header (2.54mm pitch) and shorting block (LK1) 1 TO-220 micro-flag heatsink (Jaycar HH8502, Altronics H0630) 1 M3 x 10mm machine screw 1 M3 nut 1 M3 washer 1 8-pin DIL socket 2 14-pin DIL sockets 2 16-pin DIL sockets 1 28-pin narrow DIL socket 1 32-pin DIL socket 4 No.9 x 6mm self-tapping screws 1 300mm length 0.7mm diameter tinned copper wire Semiconductors 1 dsPIC33FJ64GP802 or dsPIC33FJ128GP802 16-bit microcontroller programmed with 0121211A.hex (IC1) 1 AS6C4008 4Mbit SRAM (IC2) 2 74HC595 octal serial-to-parallel latch ICs (IC3, IC4) amount of time in SRAM buffer IC2, IC1 then retrieves the audio data and sends it to TOSLINK transmitter TX1 and also via buffer IC6 to the coax output, CON3. An 8MHz crystal oscillator provides timing for microcontroller IC1. IC1 uses an internal PLL to generate its 40MHz instruction clock, which is also used to compute the audio delay time. Circuit description Refer now to the circuit diagram (Fig.3). This shows the operation 1 74HC00 quad NAND gate CMOS IC (IC5) 1 74HCU04 unbuffered hex inverter CMOS IC (IC6) 1 LM393 dual low-power comparator (IC7) 1 DIR9001 S/PDIF decoder IC [TSSOP-28] (IC8) 1 TOSLINK transmitter (TX1) (Jaycar ZL3000, Altronics Z1603) 1 TOSLINK receiver (RX1) (Jaycar ZL3003, Altronics Z1604) 1 infrared receiver (IRD1) (Jaycar Z1611A, Altronics ZD1952) 1 7805 5V 1A linear regulator (REG1) 1 LM3940IT-3.3 3.3V 1A lowdropout linear regulator (REG2) 1 1N4004 1A diode (D1) 3 1N4148 signal diodes (D2-D4) 1 3mm green LED (LED1) 1 3mm yellow LED (LED2) Capacitors 4 100µF 16V electrolytic 1 47µF 25V electrolytic 1 10µF 16V tantalum or SMD ceramic (3216/1206) 1 150nF MKT 15 100nF MKT 1 68nF MKT 1 4.7nF MKT 2 100pF ceramic 2 33pF ceramic Resistors (0.25W, 1%) 1 1MΩ 2 300Ω 2 100kΩ 1 240Ω 3 10kΩ 1 110Ω 1 2.2kΩ 2 100Ω 1 1kΩ 1 82Ω 2 680Ω 2 10Ω in greater detail. The S/PDIF signal from CON2 is AC-coupled by a 100nF capacitor and applied to the input of CMOS inverter IC6a which is operated in linear mode using 10kΩ and 100Ω feedback resistors. Diodes D2 and D3 clamp the signal voltage in case a higher-level signal is accidentally applied to CON2. The 82Ω resistor to ground, in combination with the loading of the amplifier, provides the correct 75Ω termination. In the past, we used a 300Ω resistor here, the assumption being that 300Ω December 2011  29 +3.3V 100nF 10 32 16 Vdd Q0 Q1 11 Q2 SRCK Q3 14 IC3 Q4 SD 74HC595 Q5 12 LCK Q6 Q7 13 OE Q'7 Vss +5V 100 MR 1 2 3 9 31 30 28 27 26 25 23 1 2 4 5 6 7 9 3 4 5 6 7 8 8 16 Q0 Q1 11 Q2 SRCK Q3 14 IC4 Q4 SD 74HC595 Q5 12 LCK Q6 Q7 13 OE Q'7 Vss 100nF 15 1 2 3 22 CE 24 OE 29 WE 12 A0 11 A1 A2 10 10 1k 1 17 16 15 6 7 11 9 14 18 RB15' 21 RB3' 3 IRD1 IC2 AS6C4008 4 5 8 22 3 1  26 7 2 2 +3.3V K S/PDIF INPUT 100nF 100 A K 82 D3 IC6a 1 2 3 14 4 IC6b 10k K 20 21 28 100F 1 680 19 14 100nF 13 8 RXIN FMT1 FMT0 RST CKSEL RSV SC 2011 100nF Vcc IC8 SCKO DIR9001 FILT PSCK1 RB14 RB4 RB13 RB5 RB12 RB9 RB10 RA4 RB11 RA3 25 24 23 12 10 RA1 RB15 RB3 RA0/AN0 4 RB2/AN4 100F 25 26 4 5 CLKI 680 XT1 23 DGND 6 RB1/AN3 22 PSCK0 AGND 2 6 24 5 Vdd 100nF L1 100H 100nF RB7 RB6 IC1 dsPIC33FJ64GP802 INPUT SELECT A 3 MCLR Vdd AVdd RB8 +3.3V TOSLINK RX PWR LK1 +5V +3.3V D4 RX1 TOSLINK RECEIVER 100nF 28 RB0 S1 A +5V 13 100nF IC6: 74HCU04 D2 CON2 100nF 16 D0 D1 D2 D3 D4 D5 D6 D7 Vdd MR A3 A15 A17 A13 A8 A9 A11 A10 A18 A16 A14 A12 A7 A6 A5 A4 13 14 15 17 18 19 20 21 10 100nF 100nF 15 4.7nF 68nF 10F TANT 20 9 Vcap Vss 8 AVss 27 Vss 19 DIGITAL AUDIO DELAY 30  Silicon Chip siliconchip.com.au REG2 LM3940IT–3.3 +3.3V OUT 100nF 100F IN GND REG1 7805 OUT 10 IN GND 100F D1 1N4004 K A + – 47F CON1 9V-12V DC INPUT IC5: 74HC00 14 3 +5V IC5a 1 6 2 IC5b 5 4 10k 100nF ON A A LED1 10k K 100k RB15' K 300 8 3 300 1 IC7a 2 LOCK  LED2  IC7: LM393 100pF 5 100k RB3' IC7b 6 7 4 100pF L2 100H +3.3V 2 100nF TX1 3 TOSLINK OUTPUT 1 9 11 13 IC6d IC6e IC6f 8 10 150nF CON3 240 S/PDIF OUTPUT 110 12 7 5 IC5: 74HC00 IC6c 6 A 8 IC5c 7 9 11 10 2.2k 33pF IC5d D2, D3, D4: 1N4148 D1: 1N4004 1M A K K 12 13 IRD1 LEDS X1 8.0MHz 33pF K A 1 2 3 7805, LM3940IT-3.3 GND IN GND OUT Fig.3: the complete circuit for the Digital Audio Delay. Digital audio is fed in via TOSLINK receiver RX1 or via S/PDIF input CON2 (coax). The CON2 signal is amplified by IC6a & IC6b and fed to switch S1 which then selects between the two digital inputs. S/PDIF decoder IC8 is used to recover the clock signal. Microcontroller IC1 runs the show, buffering the audio data in SRAM IC2. IC3 & IC4 drive 16 out of 19 address lines and are controlled by serial signals from IC1. After a suitable delay, the audio is sent from IC1 to TOSLINK transmitter TX1 and via buffers IC6d-IC6f to CON3 for coaxial output. Infrared control is handled by IRD1 while LED1 & LED2 show status. siliconchip.com.au December 2011  31 What Are S/PDIF And TOSLINK? The acronym S/PDIF (or SPDIF) stands for Sony/Philips Digital Interface. Basically, it is a standardised serial interface for transferring digital audio data between consumer-level equipment such as DVD and CD players, DAT and DVD recorders, surround-sound decoders and home-theatre amplifiers. S/PDIF is very similar to the AES3 serial digital interface used in professional recording and broadcasting environments. In operation, each digital audio sample (16-24 bits) is packaged along with status, control and error-checking information into a 32-bit binary word. This is then modulated or encoded into a serial bitstream using the Biphase Mark Code (BMC). BMC involves combining the data bits with a clock signal of twice the data bit rate, in such a way that a binary “1” results in two polarity reversals in one bit period, while a binary “0” results in a single polarity reversal. This double bit-rate signal is self-clocking at the receiving end and has no DC component. The BMC encoded serial bitstream is then transmitted as a 400mV peak-to-peak signal along a single 75-ohm coaxial cable. In most cases, the cable connectors used are standard RCA or “Cinch” connectors, as also used for analog audio and composite video. Although originally developed for conveying linear PCM (LPCM) digital audio signals as used in CD and DAT audio, S/PDIF has also been adapted for conveying compressed digital audio, including Dolby Digital (AC-3), DTS and MPEG-2 audio. TOSLINK is essentially just the S/PDIF signal format converted into the optical domain, for transfer along optical-fibre cables. The accompanying table (see above) shows the most common domestic audio bitstream formats and the S/PDIF/TOSLINK bit rates for each one. Note that LPCM audio is rarely used for DVD-Video, because even a stereo audio track requires a BMC bit rate of 6.1Mb/s. Many current-model DVD players and recorders are provided with either coaxial S/PDIF or TOSLINK digital audio inputs and outputs, or quite often a mixture of both. Similarly, many hometheatre amplifiers are provided with coaxial S/PDIF and/or in parallel with 100Ω is 75Ω. But that assumes that the input to the inverter is held at “virtual ground”, which it isn’t (its output swing isn’t large enough). The output of IC6a is “squared up” by inverter IC6b and then fed to input RB2 (pin 6) of microcontroller IC1. The software sets this to be the DCI module data input. It also goes to pin 20 of IC8 (RXIN) which generates a synchronised clock signal. If S1 is in the alternative position, the S/PDIF signal to IC1 instead comes from TOSLINK receiver RX1. It is powered from either 5V or 3.3V (depending on the receiver), as set by LK1. Its supply passes through an LC low-pass filter (100µH/100nF) since it is sensitive to supply noise. If a 5V TOSLINK receiver is used, the output is 5V peak-to-peak which 32  Silicon Chip TOSLINK inputs. This is also the case with many up-market PC sound cards. Fig.4 shows the S/PDIF protocol in detail. The data is transmitted with biphase mark coding (BMC). Compare the encoded data to the raw data shown above it. The BMC has a level transition between each bit and an additional transition in the middle if the data is a one (high). So essentially, it is a form of frequency shift keying (FSK). This results in a signal with an average voltage of half the peak-to-peak amplitude. Also, the clock and data are encoded in a single stream, allowing transmission over coaxial cable. BMC data can be inverted without effect since only transition timing matters. The disadvantages are increased transmission frequency (twice the bit rate) and the hardware to recover the clock signal is somewhat complex, generally involving a phase-locked loop (PLL). The S/PDIF protocol consists of an endless sequence of “frames”. Each frame contains two sub-frames, which carry the biphase-coded audio samples for the left and right channels (multi-channel formats are explained below). Each sub-frame starts with a preamble which is not in BMC format (but has zero DC offset). Preambles “X” and “Z” are used to indicate the start of a left-channel subframe while preamble “Y” indicates a right-channel subframe. Without the preambles, it would be impossible to know where the data starts and ends. The following data consists of 24 bits of audio data (in some cases, the lowest four bits are used to store other information) plus four status bits. The “valid” bit indicates whether the preced- is clamped to 3.3V by IC1’s input clamp diode. The 680Ω series resistor limits the current under this condition to about 2mA. It also forms an (unwanted) RC filter with the input capacitance of both IC pins and stray PCB capacitance. This distorts the square wave but not enough to cause any problems. Clock recovery As explained earlier, IC8 is used solely to recover the clock of the S/ PDIF signal, allowing IC1 to sample the serial stream at the correct points. Its other functions (audio data extraction, status output, etc) are not needed and so none of its data outputs are used. IC8 requires a power-on reset (by pulling RST-bar low) and this is provided by a 100nF capacitor, a pull-up resistor (inside IC8) and diode D4. Initially, the capacitor is discharged and so RST-bar is low. The capacitor charges via the internal 51kΩ resistor and so eventually RST-bar goes high and IC8 operates normally. When the power supply is removed, the capacitor rapidly discharges via D4 and the process can then repeat. IC8 also requires a PLL filter from pin 22 (FILT) to pin 23 (AGND), comprising two capacitors and a resistor. This is a “Type II” compensation network which limits the rate at which the voltage controlled oscillator’s output frequency changes. This stabilises the PLL so it doesn’t “hunt” around the correct frequency or overshoot too much. For more information on Type II compensation networks, see page 3 of Intersil Technical Brief TB417.1 (http:// siliconchip.com.au LEFT CHANNEL SAMPLE (16-24 bits, zero padded) LEFT CHANNEL HEADER ('Preamble Z') TIMESLOTS 0 1 2 3 RAW DATA 4 MSB 5 6 1 0 0 7–24 Valid STATUS BITS RIGHT CHANNEL HEADER Channel ('Preamble Y') User Parity 25 26 27 LSB 28 29 30 31 1 0 1 0 0 1 0 32 33 34 35 RIGHT CHANNEL SAMPLE (16-24 bits, zero padded) 36 37 MSB 1 0 38 39–56 1 Valid STATUS BITS Channel User Parity 59 60 LSB 61 62 63 1 0 1 1 1 1L 1R 2L 2R 3L 3R X Y X Y X Y 57 58 1 0 0R Y BMC CODED DATA FRAME PREAMBLE 0L 0R 1L 1R 2L 2R 3L 3R Z Y X Y X Y X Y 188L 188R 189L 189R 190L 190R 191L 191R 0L X Y X Y X Y X Y Z Fig.4: the S/PDIF digital audio format. Each frame takes 64 time slots and contains up to 24 bits of audio data and four status bits for each channel. The data is biphase mark coded and two preambles are added, to distinguish the two channels. There are 192 frames per block and the blocks repeat endlessly. ing data is an audio sample or something else while the “parity” bit allows transmission errors to be detected. There are 192 frames in each “block” and one block follows another. The start of the block is indicated by Preamble X (instead of Preamble Z). This allows the other two status bits, “user” and “channel” (channel status), to be interpreted as 24 bytes of data per channel. The channel status data is interpreted differently for S/PDIF (consumer) and AES3 (professional). In either case, it contains information such as the audio format, sample rate, channel relationship and so on. The meaning of the “user” bits is applicationspecific. Multi-channel formats Formats such as Dolby Digital (AC3) and the Digital Theatre System (DTS) use digital audio compression. So despite the extra channels, the data rate is usually lower than linear PCM (see table). This data is normally transmitted in place of the audio samples with zeros to pad it out to the same size (and thus transmission rate) as linear PCM. This relies on the home-theatre receiver recognising the comwww.intersil.com/data/tb/tb417.pdf). The desired output clock rate (128 times the sample rate) is selected by tying the PSCK0 and PSCK1 pins (pins 13 & 14) to ground. The clock signal is available from pin 4 (SCKO) which is connected to pin 5 of IC1 (RB1), the DCI module clock input. SRAM interface Microcontroller IC1 interfaces with the AS6C4008 SRAM (IC2) using 14 pins. RB4-RB11 form the 8-bit bidirectional data bus. The order of connection doesn’t matter since the bits are always received in the order they were sent. Since RB4-RB11 are contiguous, the software can set or read them all in a few clock cycles. The three lowest address bits, A0-A2 (pins 10-12), are controlled directly by siliconchip.com.au pressed data and interpreting it accordingly; if it is treated as linear PCM, the result is loud static. Note that newer surround-sound formats such as Dolby Digital EX and DTS-HD use higher data rates that may in some cases exceed that of linear PCM. So the Digital Audio Delay unit may or may not handle them. Finally, Fig.5 shows how the data stream is carried by coax cable. The transmitter normally produces around 1V peak-to-peak but because the receiving end is terminated with 75Ω (to match the cable impedance), this voltage divider reduces the received signal to around 0.5V. It therefore needs amplification before it can be treated as a standard digital signal. 0V TRANSMIT NOMINALLY 1.0–1.2V RECEIVE 0.5–0.6V (MIN. 0.2V) Zo = 75 Fig.5: S/PDIF is transmitted over 75W coaxial cable with a nominally 1V peak-to-peak square wave, centred on 0V. With correct 75W termination, the receiver gets around 0.5V peak-to-peak. IC1 (pins 23-25, RB12-RB14). IC1 can therefore read or write eight bytes in quick succession. To access a different set of eight bytes, it sets the 16 remaining address pins (A3-A18) using octal serial-to-parallel latches IC3 & IC4. These are controlled with a 3-wire serial bus from IC1’s pins RB3 (pin 7, clock), RB15 (pin 26, data) and RA1 (pin 3, latch). To set a new upper address, RA1 goes low and then 16 bits of data are output. The transmitted bits first shift into IC4’s latches and then pass from its Q7 cascade output to IC3’s serial input. When RA1 subsequently goes high, outputs Q0-Q7 of IC3 and IC4 switch to the new address. Because the shifted data is held in separate latches (within IC3 & IC4) until RA1 goes high, the next address can be transferred while data at the previous address is being read/written. So while the serial addressing is slower than parallel addressing, in reality it doesn’t make much of a difference to the access speed for large blocks of data. IC2’s WE-bar, OE-bar and CE-bar lines (pins 29, 24 & 22) control the read and write cycles. For a read, the address line states are set and then both OE-bar (output enable) and CEbar (chip enable) go low. The value of that byte can then be read from the data bus. To write a byte, both the address and data line states must be set and then WE-bar (write enable) and CE-bar are brought low. After a brief period, the write is completed and these lines can go high again. To free up one of IC1’s pins, NAND December 2011  33 X1 8MHz D1 01212111 100nF 4004 9V DC INPUT 33pF IC4 74HC595 2.2k 1M 33pF 100nF 11121210 yaleD oDelay iduA latigiD Digital Audio CON1 IC5 74HC00 IC3 74HC595 S/PDIF OUT CON3 100nF 100nF + 10F TANT. 100nF D3 680 68nF 4.7nF 100 300 300 100pF 100nF 100k 100F + 4148 D4 100pF 100nF ' 2011 1102 © 100nF IC6 74HCU04 10k 82 D2 100nF 100F + S/PDIF IN 100 CON2 100nF 4148 680 100nF S1 4148 INPUT SELECT 5V 100nF 100nF REG2 IT-3.3 LM3940IT-3.3 LM3940 10k 100k 150nF RX1 IC1 dsPIC33FJ64GP802 IC7 LM393 REG1 7805 L1 100F 100H LK1 100F 3.3V + + IC8 (UNDER) 100nF 47F 10 TX1 TOSLINK IN IC2 AS6C4008 10 1k TOSLINK OUT 240 L2 100H 110 IRD1 LED2 K A LED1 K 10k A 100nF VIEWED FROM ABOVE IC 8 DIR9001 Fig.6: follow this overlay diagram to build the PCB. Note that the wire links shown will not be necessary if the PCB supplied is double-sided. Set jumper LK1 to 5V for the Jaycar and Altronics TOSLINK receivers specified (the Altronics receiver can also run of 3.3V) and check the data sheet for other types. VIEW ED FROM BELOW Fig.7: this diagram shows how the DIR9001 S/PDIF decoder IC is mounted on the copper side of the PCB – see text for details. If you inadvertently bridge two or more of the pins, the excess solder can be removed using solder wick. gates IC5a and IC5b drive the chip enable (CE-bar) line. These control it so that if either WE-bar or OE-bar go low, so does CE-bar. IC5b performs the NAND function and its output is inverted by IC5a, converting it to an AND operation. The other two sections of IC5, IC5c and IC5d, also function as inverters and form an oscillator with crystal X1. The 8MHz output is then used by IC1 to provide its 40MHz instruction 34  Silicon Chip clock which is also used for timing the S/PDIF signal. IC1 has an internal crystal oscillator but it requires the use of two micro pins while an external clock source only ties up one. S/PDIF output IC1 routes its DCI serial output to pin 4 (RB0) which is connected to the input of TOSLINK transmitter TX1. Like RX1, its power supply has an LC low-pass filter to provide glitch-free operation. Most TOSLINK transmitters run off 3.3V so we haven’t provided a 5V supply option in this case. The output signal also goes to the inputs of inverter stages IC6d-IC6f, connected in parallel for more output current as they drive a relatively low impedance (300Ω). The 150nF capacitor AC-couples the output so that it is symmetrical about ground while the 240Ω and 110Ω resistors reduce the signal amplitude to about 1V peakto-peak. They also set the output impedance to 75Ω, which matches the expected cable impedance. Unused inverter IC6c has its input connected to ground. User interface Infrared control signals are received by IRD1. Its power supply is low-pass filtered with a 100Ω resistor and 100nF capacitor because it too contains sensitive analog circuitry. Its output is fed to IC1’s RA0 digital input (pin 2). An infrared signal triggers a software interrupt and the software then decodes the received RC5 pulses and takes appropriate action. While IRD1 runs off 5V and IC1 off 3.3V, no current-limiting resistor is used between them since IRD1’s output is pulled high by a relatively high-value internal resistor (normally 10-47kΩ). Thus the current into IC1’s siliconchip.com.au The PCB assembly fits into a low-profile instrument case which can be spray-painted matte black to match other audio gear. In addition, the front and rear panels are replaced with new PCB panels which have all the necessary holes plus screened lettering on a dark blue solder mask background. clamping diode is inherently limited. Feedback to the user is via LEDs1 & 2. The micro pins controlling these LEDs are shared with the serial address bus. Because this bus (to IC3 and IC4) is not always in use, IC1 can “idle” the serial data and clock lines high (3.3V) or low (0V). Since they are idle for much of the time, this determines their average voltage. These average voltages are filtered using 100kΩ resistors and 100pF capacitors. The filtered voltages are compared by IC7, a dual comparator, to a halfsupply (1.65V) reference derived from two 10kΩ series resistors. The LM393 runs off 5V so that it can handle input voltages of up to 3.5V. If the average voltage of either RB15 or RB3 is above 1.65V, the corresponding open-collector output of the comparator (pin 1 or pin 7) goes low, turning on LED1 or LED2 respectively. So the idle state of RB15 controls LED1 (high = on, low = off) and likewise, RB3 controls LED2. The 300Ω current-limiting resistors set the LED current to about 10mA. Power supply The power supply uses linear regulators to derive 5V (REG1) and 3.3V (REG2) supply rails from a 9-12V DC plugpack. Diode D1 (1A) provides reverse polarity protection while a siliconchip.com.au 10Ω series resistor slightly reduces the dissipation in REG1. REG1 has a small flag heatsink, allowing supply voltages up to 12V (nominal). REG1 is a standard linear regulator while REG2 is a 1A 3.3V low-dropout regulator. These are fussier about their output capacitor but any decent 100µF electrolytic will be suitable (with an ESR in the range of about 0.05-2Ω). Each IC in the circuit has a 100nF MKT supply bypass capacitor, located as close to its supply and ground pins as possible. These prevent each IC’s supply voltage from sagging briefly when internal switching causes it to draw brief but relatively high current pulses. IC1 has an additional bypass capacitor for its AVdd analog supply (pin 28), with a 10Ω series resistor for better smoothing. A 10µF tantalum capacitor on pin 20 (Vcap) filters the output of its internal 2.5V regulator, from which its core runs. Since tantalum capacitors can have poor reliability, we have made provision for a 10µF surfacemount ceramic capacitor as well. IC8 also has two bypass capacitors, one for Vdd (its digital supply) and one for Vcc (analog supply), both 3.3V. These also have parallel 100µF electrolytic capacitors to stiffen its supply at lower frequencies (up to a few hundred kHz). Finally, IC1 has a 1kW pull-up resistor on its MCLR-bar (reset) pin to prevent spurious resetting due to electrical noise. Construction The Digital Audio Delay is built on a 103 x 118mm PCB coded 01212111 – see Fig.6. This fits into a low profile instrument case (140 x 110 x 35mm). The first step is to solder the SMD IC (IC8) in place – see Fig.7. It is in a 28pin TSSOP (thin shrink small outline package) device with a pin pitch of 0.65mm. It isn’t too difficult to solder with the right tools. If you are building it from a kit and the SMD IC is already in place, skip to the next section. Place the PCB copper-side up and apply a very small amount of solder to the upper-right pad with a clean soldering iron (use a medium to small conical tip). If you are left-handled, start with the upper-left pin instead. That done, pick up the IC with tweezers (the angled types work well) and position it near the pads with the correct orientation, ie, its pin 1 dot positioned as shown on Fig.6. Heat the tinned pad, slide the IC into place and remove the heat. Check its alignment carefully (use a magnifying glass if necessary). It should be straight, with all the pins over their respective pads and an equal December 2011  35 How The Software How The Works Software Works A S WITH MANY projects involving microcontrollers, a lot of the effort has gone into the software. The hardest part were the routines to lock onto, decode and re-encode the S/PDIF stream in real time, with enough cycles left over for SRAM reading/writing, infrared decoding, etc. When the DCI (data converter interface) peripheral is activated, it starts receiving the S/PDIF data into RAM buffers, starting with whichever bit happens to come along first. While an audio block is an integer multiple of the buffer size, there is no guarantee of proper alignment; in fact the chance of this happening is very low (see Fig.8). We initially tried a number of methods to “re-align” the hardware buffers to the S/ PDIF stream but these turned out to be slow and unreliable. Instead, the alignment is done by the software. It scans each received buffer for a valid preamble, one bit at a time. If it finds one, it stores that bit offset and looks at the same position in the next buffer. If the preamble appears in the same position in subsequent buffers, the software has locked onto the S/PDIF stream. It can then shift the bits when copying from the DMA buffers into the local RAM buffers, realigning it as required by the decoding function. To speed up decoding, several RAM look-up tables are generated at start-up. It’s then just a matter of using the BMCcoded data as an index into that table, one byte at a time, to retrieve the decoded equivalent. The re-encoding process uses a different table in a similar way. The main program loop constantly transfers decoded data to the SRAM amount of exposed pad on either side. If not, reheat the solder joint and gently nudge the chip in the right direction. Repeat until its position is perfect then solder the diagonally opposite pin. Re-check the orientation and readjust it if necessary before soldering the remaining pins. Don’t worry too much about solder bridges; they are virtually inevitable and can be easily fixed. The most important job now is to ensure that the solder flows onto all pins and pads. That done, apply a thin smear of no-clean flux paste along all pins and remove the excess solder using solder wick. Once the flux is heated to boiling point, this should happen quickly. Be 36  Silicon Chip S/PDIF S/PDIF BLOCK BLOCK BUFFER BUFFER BITS BITS 0L 0L 0R 0R 1L 1L LAST TRANSFER LAST TRANSFER 0 0 1 1 2 2 3 3 BUFFER 1 1R 1R 4 4 5 5 2L 2L 2R 2R 3L 3L 3R 3R 4L 4L THIS TRANSFER THIS TRANSFER 1022 1023 0 1022 1023 0 1 1 BUFFER 2 2 2 15L 15R 16L 16R 17L 17R 15L 15R 16L 16R 17L 17R 4R 4R 3 3 4 4 5 5 BUFFER 3 NEXT TRANSFER NEXT TRANSFER 1022 1023 0 1022 1023 0 1 1 2 2 3 3 4 4 5 5 BUFFER 4 1 BUFFER 2 BUFFER 4 BUFFER 3 Fig.3:BUFFER there’s no easy way to align the S/PDIF data with the DCI receiver Fig.8: there’s no easy way to align the S/PDIF data with the DCI receiver buffers so it’s normally offset. As a result, the S/PDIF blocks usually start in buffers so it’sofnormally a result,for theby S/PDIF blocks usually start in the middle a buffer. offset. This isAs corrected the software, which scans the the middle a buffer. This issequence corrected forthen by the software, which the buffer for aofvalid preamble and shifts the data into scans alignment. buffer for a valid preamble sequence and then shifts the data into alignment. (IC2). At the same time, it reads back data from a different location and re-encodes it, inserting the appropriate preambles. This then goes to one of four outgoing buffers, which are transferred into DMA space when appropriate by an interrupt handler, to be serialised and transmitted. Writing to flash Since this microcontroller has no EEPROM (electrically erasable programmable read-only memory), the delay must be stored in flash memory. Microchip provide an EEPROM emulation library to do this but using it caused a glitch in the audio output each time the delay value was changed. It turns out that their function waits for the flash write to complete before reenabling interrupts and returning program control to the main loop. This means that the DMA interrupt handlers can’t feed data to the DCI for that period and this is long enough to cause a drop-out. We increased the DMA buffer size but it didn’t solve the problem. In the end, we wrote our own EEPROM emulation funcsure to trim the end off the wick if it gets solder-logged. You should now make a final and careful inspection to ensure that there are no remaining solder bridges and that the solder has not balled on the lead without flowing onto the pad. If there are still bridges, clean them up with more flux and solder wick. Through-hole parts Now install the 14 wire links using 0.7mm diameter tinned copper wire. Follow with the resistors, checking each with a DMM to ensure the correct value is used in each case. Fit the three 1N4148 small signal diodes (D2-D4) next, with the orienta- tions, which have the following differences: • Two 12-bit values stored per program word, rather than one, increasing flash memory life. • Simpler logic (since there’s only one value to store), speeding up the write function. • Virtually all page erases are done at start-up to avoid extra delays during operation. Interrupts are re-enabled and control returned to the program as soon as the write is initiated. Our software includes a timer to delay subsequent updates to avoid problems (and to minimise the number of writes). We also changed the code to always do the flash writes just after a new DMA buffer has been fed to the DCI unit. This is the time at which the DCI buffer is most full, giving the flash write as much time to complete as possible before the buffer needs to be refilled. That solved the problem. We don’t have room here to describe the software in full. The source code is available in a ZIP file from the SILICON CHIP website. tion as shown on the overlay diagram (cathode stripes to the top). Then install diode D4 (1N4004) at upper left with the opposite orientation. Next up are the two axial inductors L1 & L2 and then the IC sockets. Make sure the notches for the sockets go either to the left or to the top – see Fig.6. That done, mount the four ceramic capacitors and then the MKTs, starting with the 4.7nF, 68nF and 150nF where shown (the rest are all 100nF). The electrolytic and tantalum capacitors can then go in. The tantalum type should have a “+” symbol on the body and it must be orientated as shown (towards the left). If you are using an SMD ceramic instead, it goes siliconchip.com.au on the underside of the PCB. For the aluminium electros, the longer lead goes towards the side marked “+”. Don’t get the 47µF and 100µF types mixed up. Crystal X1 is next on the list and then the connectors and slide switch can go in, starting with the lowest profile part. Ensure they are all flat against the PCB and parallel to the edge before soldering them. LK1 goes in next, with a shorting block (jumper) fitted to suit your TOSLINK receiver: 5V for the Jaycar ZL3003 and either 3.3V or 5V for Altronics Z1604 (for others, check the data sheet). The leads for the LEDs and infrared receiver (IRD1) need to be cranked before they can be installed. Bend the LED leads down 5mm from the lens, so that the anode (longer lead) will go into the pad closest to the bottom edge of the PCB. Mount them with the horizontal portion of the lead 7mm above the PCB (a 7mm-wide strip of cardboard can be used as a spacer). Now for IRD1. Bend its leads backwards through 90° 2mm from its body, then back down again 5mm behind that. It then goes in with the horizontal lead section sitting on top of the PCB. Regulators Before installing REG1 (7805), fit the small flag heatsink to its tab as shown on Fig.6, with a washer under the screw head. That done, solder it to the PCB with the tab towards the top. REG2 goes in the opposite way (it doesn’t need a heatsink). The PCB assembly can now be completed by plugging the ICs into their sockets, ensuring that the notch/ dot is orientated as shown in each The Jaycar AR1729 remote – program it with code 916 for a Philips VCR. The Altronics A1012 remote – it’s programmed with code 115 for a Philips VCR. case. Be careful not to get IC5 and IC6 mixed up. Housing it If using the recommended case, you may wish to spray-paint the top and bottom pieces matte black, as we did. We lightly glued a couple of empty wire reels to the underside of the lid and base to act as stands. We then sprayed both with one coat of primer and then three thin coats of flat black. You can get a better finish if you do this indoors (eg, in a garage) but if you do this you will need to make a spray booth (eg, a large cardboard carton). The front and rear panels shown in the photos are actually PCBs with blue solder masks and white screened lettering. These are mechanically strong, look good, are relatively cheap and the Table 1: Resistor Colour Codes o o o o o o o o o o o o o siliconchip.com.au No.   1   2   3   1   1   2   2   1   1   2   1   2 Value 1MΩ 100kΩ 10kΩ 2.2kΩ 1kΩ 680Ω 300Ω 240Ω 110Ω 100Ω 82Ω 10Ω 4-Band Code (1%) brown black green brown brown black yellow brown brown black orange brown red red red brown brown black red brown blue grey brown brown orange black brown brown red yellow brown brown brown brown brown brown brown black brown brown grey red black brown brown black black brown labels and cut-outs are already done for you. It’s just a matter of slipping them onto the ends of the PCB assembly, then slotting the whole assembly into the case and screwing the board down using four self-tapping screws. The lid can then be attached. Testing If you have a bench supply, set the Table 2: Capacitor Codes Value 150nF 100nF 68nF 4.7nF 100pF 33pF µF Value 0.15µF 0.1µF 0.068µF .0047µF   NA   NA IEC Code EIA Code 150n 154 100n 104   68n 683   4n7 472 100p 101   33p   33 5-Band Code (1%) brown black black yellow brown brown black black orange brown brown black black red brown red red black brown brown brown black black brown brown blue grey black black brown orange black black black brown red yellow black black brown brown brown black black brown brown black black black brown grey red black gold brown brown black black gold brown December 2011  37 The completed unit is neat and compact. There are no external controls – the delay is set using a universal remote control and once set, should not need further adjustment. output to 8V DC 200mA and apply power to CON1. If the current draw is over 150mA (typically 120mA), switch off and check for faults. If you don’t have a bench supply, simply connect the plugpack and check the LEDs. When power is applied, LED1 (green) should flash slowly four times as the micro performs an SRAM test. If a memory fault is detected, LED1 goes off and LED2 (yellow) flashes rapidly. If the SRAM is OK, LED1 turns on and stays on. If not, check for faults. Specifically, check the orientation of all polarised components: tantalum and aluminium electrolytic capacitors, diodes, LEDs, ICs and regulators. Also check that there are no solder bridges between pads on the underside of the PCB, especially around IC8. Measure both power supply rails; they should be in the range of 3.0-3.6V and 4.75-5.25V. Assuming all is well, you can connect a test signal. Be sure set S1 according to which input you use (TOSLINK or S/PDIF). Now turn on the signal source and play some media. When a valid signal is detected, LED2 (yellow) should turn on and stay on to indicate signal lock. If you do not get a signal lock, connect a frequency counter between the wire link running to pin 5 of IC1 and a ground point (eg, regulator tab). You should get a reading of several MHz; typically around 6.144MHz. If you get a much lower reading, 38  Silicon Chip check the frequency at the middle pin of switch S1. This should be slightly lower, around 4MHz. If this is not present, there is a problem with the S/PDIF reception circuitry. Check the power supply rails and examine the problem area for soldering faults or component problems. If there is a signal on the middle pin of S1 but not pin 5 of IC1, that suggests a problem with IC8. Check its surrounding components and the soldering of its pins. The anode of D4 should be at about 3.3V. Using it To set the delay, you need a universal infrared remote control (eg, Jaycar AR1729 or Altronics A1012), set for a Philips VCR. For the Jaycar AR1729 the code is 916 and for the Altronics A1012, use 115. For other universal Kit Availability Jaycar has indicated that they will produce a complete kit of parts for this project. This kit (Cat. KC-5506) will be supplied with screen-printed front and rear panels and with the DIR9001 surface-mount chip soldered in place. Alternatively, the PCB (without the DIR9001 IC), the front and rear panels and a programm­ ed microcontroller (dsPIC33FJ64GP802 or dsPIC33FJ­ 128GP802) are available separately from SILICON CHIP. remotes, try various Philips VCR codes until the mute button toggles the green LED. The yellow LED flickers when a valid RC5 transmission is received. You can then use the following buttons to set the delay: • 1-9: sets the delay to 100-900ms. • 0: sets the delay to 1000ms. • Channel Up/Down: increases/decreases the delay by 100ms, to a maximum/minimum of 1500/20ms. • Volume Up/Down: increases/decreases the delay by 10ms. • Mute: toggles the delay defeat (or delay bypass). The front-panel LEDs respond as follows: • Green: slow flash = testing memory; fast flash = buffering audio; on = operating; off (yellow on) = delay defeat mode. • Yellow: fast flash = memory error; on = locked onto S/PDIF signal: flicker = infrared activity. Check that the delay is turned on (green LED on) and then tune into a broadcast or play some media. Observe the delay between the picture and the sound. If the sound is “early”, increase the delay. If the sound is “late”, decrease it. Typically, you will need to delay the sound by 100-200ms. If you change the delay, it is automatically saved to internal flash memory and this is then loaded each time the unit is powered up. The defeat mode is reset on power-up, ie, it is not SC remembered. siliconchip.com.au