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By NICHOLAS VINEN Audio delay for PA systems If you have ever been in a hall or concert venue which has multiple speakers, you will know that intelligibility can be a real problem. This is caused by the different propagation times of the sounds from speakers near and far away from you. How do you fix it? By adding an audio delay. This unit does that by delaying the audio signal from the microphone by up to 640 milliseconds. But that’s just the beginning of its capabilities. It is actually a fully-fledged stereo DSP board with a 32-bit processor running at 80MHz and with appropriate software, is capable of providing other effects such as echo, reverb and compression. PA SYSTEMS IN HALLS and larger venues can often present a problem with intelligibility, especially if you are sitting up the back. Picture the situation in a large church, for example. There will typically be a pair of large column speakers up the front of the congregation but they cannot be 36  Silicon Chip turned up enough so that people up the back can hear the proceedings. So another pair of column speakers might be installed half way along or further back in the church. That should mean that people up the back can now hear what’s going on but now the sound becomes jumbled because while the sound from the speakers close to you may be loud enough, it is actually being muddied by the delayed sound from the speakers up the front. The solution is to delay the sound coming from the rear speakers and that is what this project does. In practice, siliconchip.com.au C IRCULAR STORAGE B UFFER (1MBYTE) IC3: 1MB SRAM (OPTIONAL) 8-BIT DATA BUS, 20-BIT ADDRESS BUS PARALLEL MASTER PORT (PMP) PIN 20 LEFT IN ADC OUT C IRCULAR STORAGE 2 I S DMA1 DELAY PIN 19 RIGHT IN ADC IC2 (CODEC ) DAC OUT IN DAC OUT PIN 12 LEFT 2 I S B UFFER (127KB) 65024 x 16-BIT SAMPLES OUT IN DMA2 IC1 (PIC 32 MICRO) PIN 13 RIGHT IC2 (CODEC ) Fig.1: the basic concept. The incoming audio signal is fed into the analog-to-digital converter (ADC) of CODEC IC2 and the resulting digital data then fed into a circular recording buffer which is 127kB of the static RAM on a PIC32 microcontroller (IC1). The delayed signal is then picked off from within this buffer and converted back to audio by IC2’s digital-to-analog converter (DAC) section. SRAM chip IC3 is added if you want a delay of more than 640ms. if the distance between the front and rear speakers is more than about 10 or 15 metres, an audio delay can be very worthwhile. Of course, this means that you need two separate PA systems: one for the rear speakers with the audio delay and one for the speakers at the front of the hall, church or whatever. But what if you have a much larger hall? In that case, you might need to break the PA installation into three, with two sets of audio delays. Guess what? This project can also cater for that. In the simple mode, with just one delay required, it can operate in stereo. If two audio delays are required, it can operate with two separate channels, each with their own delay. Now some PA systems can have pretty good fidelity, so we wanted to produce the audio delay(s) while adding very little distortion and noise to the signal. We also wanted the delay unit to be cheap and easy to build. The solution was to combine an all-in-one audio CODEC chip (digital COder/DECoder) with a PIC32 micro­ controller that has a digital audio interface. These two chips, plus a few support components, give a 24bit, 96kHz stereo analog-to-digital converter (ADC), a similar digital-toanalog converter (DAC) and enough siliconchip.com.au processing power and memory for quite a long delay. In fact, with its 128KB of internal RAM, the PIC32 we have chosen can provide a delay of up to 640 milliseconds. It also has a Parallel Master Port (PMP) which can interface directly with a standard static RAM (SRAM) chip. This allows us to have provision for up to 1MB of additional RAM to be used in case even longer delays are needed – up to six seconds, in fact. That could be useful in a very large venue such as a surf carnival, with speakers spread along several hundred metres of beach. We’re using a sampling rate of 48kHz and a 16-bit voltage resolution, as this gives near-optimal performance with the CODEC chip we are using while keeping memory storage requirements modest. The ADC performance is the limiting factor. By the way, the author has published two previous audio delay units but this one has features lacking in those. For example, the SportSync from May 2011 can be set for a long delay but it only has one channel (ie, mono) and its sound quality is not especially high, being intended for use with AM radio sports commentary. The second previous unit, the Digital Audio Delay from December 2011, only has digital audio inputs and outputs while this unit only has analog inputs and outputs, so they are suited for different purposes. Note that this is the first microcontroller-based audio delay we have published that does not require an external SRAM chip thanks to the large 128KB internal RAM in the PIC32. Delay concept The method of providing an audio delay is very similar to that employed in the abovementioned projects and Fig.1 shows the concept. The signal from the audio mixer is fed at line level into the analog-to-digital converter (ADC) of the CODEC. The digital data is then fed into a circular recording buffer which is 127 kilobytes of static RAM on the PIC32 microcontroller. We can then pick off the output signal from anywhere within this buffer. Depending on the sampling rate (in this case, 48kHz), the difference between when the data is written and read out determines the time delay. Of course, the delayed data signal must then be converted back to audio by the digital-to-analog converter (DAC) section of the CODEC. So in essence, only two chips are required: microcontroller IC1 (the justreleased PIC32MX470F512H) and the November 2013  37 Features & Specifications • • • • • • • • • • Adjustable stereo delay of 0-640ms (6s if optional SRAM chip fitted) THD+N <0.03% (typically <0.02%), 20Hz-20kHz (20Hz-22kHz bandwidth; see Fig.6) Signal-to-noise ratio typically >76dB Optimal input signal range 0.5-2V RMS Output signal 1V RMS Input impedance 6kΩ (DC), 4kΩ (20kHz) 7.5-12V DC plugpack supply, current drain 60-80mA Delay adjustment via internal trimpot or external control knob Uses the latest PIC32 microcontroller Future expansion can add extra modes such as echo, reverb and compression stereo audio CODEC, IC2 (WM8731). An optional static RAM (SRAM) chip (IC3)is only fitted if you want a delay of more than 640 milliseconds (see Fig.3). Circuit description Fig.2 shows the circuit with IC1 and IC2. If you look at the PCB for this project, you will notice that there is provision for many more components than are used in this circuit. One of those is IC3, which is shown in Fig.3. All the other “missing” components will be featured in future projects which will employ the same core circuit. So, referring to the top left-hand corner of the circuit, the unbalanced stereo audio signal is applied to 6.35mm jack socket CON1. If a mono plug is used, the signal will be applied to the right channel input while the left channel input will be shorted to ground. The left and right channel signals first pass through RC filters comprising 1kΩ resistors and 1nF capacitors, to remove ultrasonic and RF components which would interfere with the ADC’s operation. The signals then go into adjustable attenuators which consist of two 5kΩ trimpots, VR5 & VR6. While these can be individually adjusted, normally they would be set to give the same signal level for both channels. These attenuators are required because IC2 runs off 3.3V and thus it can only handle a signal of up to about 1V RMS (2.828V peak-to-peak) before clipping. For input signals below 1V RMS, VR5 & VR6 are set at maximum. The attenuated signals are AC-coupled to IC2’s inputs by 1µF non-polarised capacitors. In order for the signal handling to be maximised and for symmetrical clipping in the 38  Silicon Chip event of overload, the input signals are biased to half the supply voltage of 3.3V, ie 1.65V. This half-supply DC bias comes from IC2 and is fed to the line inputs at pins 19 & 20. This voltage also appears at pin 16 (VMID) where it is filtered by a pair of external capacitors for noise and ripple rejection. IC2 uses crystal X1 (12MHz) to generate an internal clock which is then divided down to produce the sampling rate for both its ADC and DAC. These dividers are configurable and are controlled by microcontroller IC1. Normally, a 12.288MHz crystal or similar would be required to get a sampling rate of 48kHz (by dividing by 256) but IC2 has a special “USB mode” designed to operate with a 12MHz clock, as used for USB communications. So we use a 12MHz crystal which is easier to get. IC2 continuously samples the two analog input signals at pins 20 & 19 and converts the voltage levels at these pins to one of 65,536 possible values (216) at 20.8μs intervals. These values are serially streamed out in digital format from pin 6. Pins 2, 3 & 5 provide the clock signals required to interpret this data. Respectively, these are the master clock (MCLK, 12MHz), bit clock (BCLK, 3.072MHz = 48kHz x 2 x 32 bits) and left/right sample clock (LRCK, 48kHz). The master clock is normally used to synchronise multiple digital audio devices in a system. In this case, we’re simply using it as a reference clock for IC1, as it has a more precise frequency than IC1’s internal oscillator. The bit clock (BCLK) is at 64 times the sampling rate because the audio data is padded to 32 bits per channel. We’re only using 16 bits per channel so half the time, this output will be zero (low) but the CODEC can be configured for 24-bit operation too, hence the higher clock rate. This clock is used by the micro to determine when a new data bit appears at the ADCDAT output. The left/right sample clock indicates the start of a new value being transmitted on ADCDAT, as well as allowing the micro to determine which channel this value is for (low = right, high = left). Since this changes twice for each sample, the frequency of this signal equals that of the sampling rate, ie, 48kHz. After receiving this data and delaying it for the appropriate amount of time, IC1 sends it back verbatim to IC2’s pin 4, the DAC input data pin. The same clocks (ie, BCLK and LRCK) are used to time this data and thus the DAC and ADC sampling rates are locked together. IC2’s internal DAC then converts the received data to voltages on pins 12 & 13 (LOUT and ROUT respectively). These signals are AC-coupled using 1µF capacitors and DC-biased to ground using 47kΩ resistors. The 100Ω series resistors isolate any cable or load capacitance from IC2’s internal op amp buffers. From there, the signals then pass to the output at 6.35mm jack socket CON2. As explained, IC2 runs off 3.3V so the maximum output signal level is limited to around 1V RMS (2.828V peak-to-peak). This is sufficient to drive virtually any amplifier or mixer. Note that the WM8731 codec has a “pass-through” mode whereby a direct analog connection is made from pin 20 (LLINEIN) to the analog buffer feeding pin 12 (LOUT) and similarly, from pin 19 (RLINEIN) to pin 13 (ROUT). We take advantage of this if the delay pot is set at minimum; in this case, there is essentially no delay and the distortion and noise from the unit drop too. Microcontroller As noted above, we chose the PIC32MX470F512H for a number of reasons. It is one of the latest PIC32 chips and as such it has two enhanced SPI peripherals which directly support all the common digital audio formats, including I2S, left-justified, right-justified and DSP modes. The WM8731 CODEC supports all these modes and we are using left-justified siliconchip.com.au 4.7Ω 2x 100 µF 1k 1000 µF 2x 100nF 1nF VR5 5k MMC 1 µF MMC 20 1 µF MMC 19 1k CON1 18 17 1nF 25 VR6 5k 26 7 6 3 2 X1 12MHz MMC 14 HPVdd AVdd LLINEIN 33pF 10k DBVdd DCVdd 21 MODE LHPOUT LOUT MICIN 9 100Ω 1 µF MMC 12 10 XTI/MCLK XTO 1 µF MMC ROUT DACLRC CODEC ADCLRC DACDAT ADCDAT SCLK BCLK SDIN CSB CLKOUT VMID HPGND AGND DGND 15 11 OUTPUT 100Ω RHPOUT IC2 WM8731 13 MICBIAS 16 33pF +3.3V 2x 100 µF 27 1 RLINEIN FB2 ANALOG GND 2x 100nF FB1 8 INPUT +3.3V CON2 5 47k 4 47k 24 23 22 28 100nF 22 µF MMC DIGITAL GND L1 100 µH +3.3V +3.3V 4x 100nF 100nF 19 DELAY 1 (VR3) VR1 10k (VR4) VR2 10k 39 40 50 51 42 55 54 48 53 52 21 49 POT1 AUX4 MCS AUX1 RD WR (OPTIONAL) DELAY 2 POT2 11 33 34 36 37 VBUSON USBID VBUS D– D+ 35 60 61 62 63 64 1 2 3 D7 D6 D5 D4 D3 D2 D1 D0 100nF 56 10 µF 26 10 AVdd Vdd CLKI/RC12 CLKO/RC15 SCK1/RD2 RPD3/RD3 RD8 RD7 RD6 RC14 PMRD/RD5 PMWR/RD4 AN8/RB8 AN24/RD1 VBUSON USBID VBUS D– D+ VUSB3V3 PMD0/RE0 PMD1/RE1 PMD2/RE2 PMD3/RE3 PMD4/RE4 PMD5/RE5 PMD6/RE6 PMD7/RE7 Vcap AVss Vdd 10k 57 38 Vdd Vdd MCLR RF1 PGED2 PGEC2 RD0 RC13 RF0/RPF0 RD9/RPD9 RB4 RB3 RB2 RB1 IC1 PIC32MX470PIC3 2 MX470- RB9/PMA7 RB10/PMA13 F512H RB11/PMA12 RB12/PMA11 RB13/PMA10 RB14/PMA1 RB15/PMA0 RD11/PMA14 RD10/PMA15 RF5/PMA8 RF4/PMA9 RB0/PMA6 RG9/PMA2 RG8/PMA3 RG7/PMA4 RG6/PMA5 Vss Vss Vss 20 9 25 7 1 2 59 18 17 46 47 58 43 12 13 14 15 22 23 24 27 28 29 30 45 44 32 31 16 8 6 5 4 3 7.5 – 12V DC INPUT K V+ D1 1N4004 A K IN LED1 5 PGED PGEC Fig.2: the basic Stereo Audio Delay circuit. The incoming stereo analog signal at CON1 is digitised by CODEC IC2 and then passed over a digital bus to IC1 which stores it in its 128KB internal SRAM. This data is later sent back across the same digital audio bus to IC2, where the DAC converts it back into a pair of analog signals which are fed to the output (CON2) 41 A OUT ADJ 10k POWER 4 REG1 LM317 3.3Ω S1 CON3 PGED PGEC CON7 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D2 1N4004 POWER A K 120Ω LED1 A 1000 µF λ +3.3V D3 1N4004 200Ω 100 µF K A 100 µF K SC  2013 AUDIO DELAY FOR PA SYSTEMS siliconchip.com.au ICSP SKT LM317T 1N4004 A K OUT ADJ OUT IN November 2013  39 +3.3V 100 µF 100nF 100nF 11 18 19 20 21 22 A19 A18 A17 A16 A15 A19 A18 A17 A16 A15 23 A14 24 A13 25 A12 26 A11 27 A10 28 A9 39 A8 42 A7 43 A6 44 A5 1 A4 2 A3 3 A2 4 A1 5 A0 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Vdd 33 Vdd IC3 R1LV0808ASB R1LV0 8 0 8 ASB GND 12 GND 34 40 6 CS1 41 OE 17 WE 38 NC 37 NC 30 NC 29 NC 16 NC 15 NC 8 NC 7 NC 36 DQ 7 35 DQ 6 32 DQ 5 31 DQ4 14 DQ 3 13 DQ 2 10 DQ 1 9 DQ 0 CS2 MCS RD WR D7 D6 D5 D4 D3 D2 D1 D0 OPTIONAL MEMORY EXPANSION Fig.3: adding a Renesas R1LV0808ASB 1MByte SRAM chip allows the delay to be increased from a maximum of 640ms up to a maximum of six seconds. It runs from the same 3.3V supply as IC1 and is driven by the Parallel Master Port (PMP) memory interface in the PIC32. mode as this allows us to set up the SPI peripheral to ignore the 16 trailing zeros for each sample. This PIC32 chip also has four very flexible DMA (direct memory access) units. These are used to copy data between other peripherals and/or RAM simultaneously while the processor is busy doing something else. In fact, they are so flexible that for a simple stereo delay, we just need to set up two DMA channels, one to read data from the CODEC and place it into a RAM buffer and another to read from a different location in that RAM buffer and send it back to the CODEC. The CPU can then go into idle mode while the DMA and SPI units do all the actual work! The processor core only needs to wake up periodically to check if the delay has been changed via the adjustment pot (using an interrupt request [IRQ]) and if necessary, adjust the DMA memory pointers to suit. The main delay adjustment pot is wired to analog input pin 21 of IC1 (AN8). Normally, this is a multi-turn trimpot so that the delay can be preset but in some cases, it may be desirable to have an externally accessible knob and so 9mm pot VR3 can be fitted instead. Provision has also been made for a 40  Silicon Chip second delay adjustment pot (VR2 or VR4). This allows the unit to provide two separate delays of the same mono signal and the delays can be set independently. This could be useful for a PA system where the speakers are placed far apart. IC1 can detect whether VR2 or VR4 is installed since it has weak pull-up and pull-down current sources/sinks on every I/O pin which can be individually enabled or disabled (+250/-50µA). IC1 turns on the pull-up and pull-down currents alternately and measures the change in voltage on that pin. Without VR2/VR4, the voltage difference will be nearly the supply voltage, ie, 3.3V. If either pot is installed, the change will be much less and so the unit knows to operate in dual mono delay mode. The MCLK signal from IC2 goes to pin 39 of IC1, which is the clock input (OSCI), while the digital audio data (BCLK, DACDAT, DACLRC & ADCDAT) connects to pins which are routed to IC1’s internal SPI/digital audio peripheral #1. This requires the bit clock to be connected to pin 50 but the other signals can go to one of several pins and are routed via its “Peripheral Pin Select” digital multiplexer. The rest of the components surrounding the microcontroller are various power supply bypass capacitors, including a 10µF capacitor at pin 56 (VCAP) which is required to filter the 2.5V core supply. This is derived from the 3.3V rail by a low-dropout regulator within IC1. There is also provision for CON7 which is a 5-pin in-circuit programming header (ICSP), with a 10kΩ pull-up resistor for MCLR-bar (pin 7) to prevent spurious resets. IC1 has a separate analog supply pin (pin 19, AVdd) for its ADC and a 100µH axial inductor is used to filter this supply. This ADC is used to sense the positions of VR1-VR4 by measuring the voltage at their wiper(s). At the time of writing, the PIC32MX470 is so new that it is only available as engineering samples but production chips should be available by the time you read this. As usual, pre-programmed chips will be available from the SILICON CHIP Online Shop. Optional memory expansion Virtually all of IC1’s 128KB internal RAM is dedicated for use as a delay buffer and should be sufficient for most applications. But if a longer delay is required, IC3 can be fitted as mentioned above (see Fig.3). This is a Renesas R1LV0808ASB 1MByte SRAM chip. It runs from the same 3.3V supply as IC1 and its memory is arranged as 8 bits x 1048576 (220). This is driven by the Parallel Master Port (PMP) memory interface in the PIC32. The PMP on this PIC32 has 16 address lines (PMA0-15), eight data lines (PMD0-7) and read/write strobe pins PMRD/PMWR. These are connected to IC3’s A0-15 address lines (in no particular order), DQ0-7 bidirectional data lines, OE-bar (output enable) and WE-bar (write enable) respectively. The PMP can be driven by one or more DMA channels to allow copying between internal and external RAM while the processor is otherwise occupied. Since a 1MB 8-bit SRAM requires 20 address lines and IC1 only has 16, the other four are driven by GPIO (generalpurpose input/output) pins 12-15 (RB1-RB4). Thus, the Parallel Master Port can read or write blocks of 64KB of memory (216), with the four GPIO pins selecting one of 16 different 64KB blocks to access at any given time. Besides the power supply pins siliconchip.com.au Parts List 1 double-sided PCB, coded 01110131, 148 x 80mm 1 ABS plastic instrument case, 155 x 86 x 30mm (Altronics H0377) 1 set front and rear panel labels 4 No.4 x 6mm self-tapping screws 1 12MHz HC-49 crystal (X1) 1 100µH axial RF inductor (L1) 1 10kΩ multi-turn vertical trimpot (VR1) OR 1 x 10kΩ 9mm horizontal potentiometer (VR3) 2 5kΩ horizontal mini trimpots (VR5,VR6) 2 6.35mm PCB-mount stereo switched jack sockets (CON1,CON2) (Jaycar PS0195, Altronics P0099 or P0073) 1 5-way pin header, 2.54mm pitch (CON7) 1 PCB-mount SPDT right-angle toggle switch (Altronics S1320) 1 DC plugpack, 7.5-12V, 100mA+ 2 4mm ferrite suppression beads (which are bypassed with one electrolytic and two ceramic capacitors), the only remaining pins on IC3 are two chip select lines, CS1-bar and CS2. With CS2 permanently tied to +3.3V, CS1-bar controls whether IC3’s interface is active and this is driven by GPIO pin 54 (RD6) of IC1 (active-low). IC1 can detect whether IC3 is present simply by attempting to use it. With weak internal pull-downs enabled on the data bus, it will simply read zeros if IC3 is absent so we just need to do a test write to verify that it is connected and operating normally. If so, the delay adjustment range is set as 0-6s rather than 0-645ms. Note that when using a RAM chip such as this, the order in which the data and address lines are connected doesn’t matter. All that really matters is that when you write data to a particular address and then read that same address later (ie, all the address lines are in the same state), you get the same data back. Any jumbling of the address or data lines in a write operation is automatically reversed during a read. This is in contrast to DRAM (dynamic RAM), where the memory is broken up into rows and columns, and it’s much faster to access data sequentially than at random. SRAM is more akin to a large register file and in general, siliconchip.com.au 1 PCB-mount switched DC socket to suit plugpack 1 M3 x 6mm machine screw and nut Semiconductors 1 PIC32MX470F512H-I/PT 32-bit microcontroller programmed with 0111013A.hex (IC1) (available from SILICON CHIP Online Shop) 1 WM8731SEDS or TLV320AIC23BIPW 24-bit 96kHz stereo CODEC (IC2) (element14 1776264) 1 LM317T adjustable regulator (REG1) 1 3mm blue LED (LED1) 3 1N4004 diodes (D1-D3) Capacitors 2 1000µF 25V electrolytic 6 100µF 16V electrolytic 1 22µF 16V electrolytic performance is identical regardless of the address pattern used during read or write operations. Power supply Toggle switch S1 switches power, while diode D1 provides reverse polarity protection. A 3.3Ω resistor limits the inrush current and REG1 provides a regulated output of 3.15-3.55V (nominally 3.35V), programmed with the 120Ω and 200Ω resistors. Diodes D2 & D3 protect REG1 against its input being suddenly shorted (however unlikely that is), while the capacitor at D3’s anode improves high-frequency supply ripple rejection. Blue LED1 is the power indicator and its current-limiting resistor is used to run it at 0.4-0.8mA, depending on the incoming supply voltage. As well as the aforementioned supply bypass capacitors for microcontroller IC1 and optional SRAM IC3, there are also a number of bypass capacitors for IC2. Each of its various supply pins has a 100nF ceramic and 100µF electrolytic capacitor to ground. There is also a low-pass filter for its analog supply pins, to reduce the amount of supply noise that might be coupled from the digital circuitry. This is necessary to get good analog performance, especially for the ADC. 1 10µF 6.3V 0805 SMD ceramic 4 1µF 50V monolithic ceramic 11 100nF 6.3V 0805 SMD ceramic 2 1nF MKT 2 33pF ceramic disc Resistors (0.25W, 1%) 2 47kΩ 1 120Ω 3 10kΩ 2 100Ω 2 1kΩ 1 4.7Ω 0.5W 5% 1 200Ω 1 3.3Ω 0.5W 5% Extra parts for longer delay 1 R1LV0808ASB-5SI 8MBit 3.3V SRAM (IC3) (element14 2068153) 1 100µF 16V electrolytic capacitor 2 100nF 6.3V 0805 SMD ceramic capacitors Extra parts for dual mono delay 1 10kΩ multi-turn vertical trimpot (VR2) OR 1 x 10kΩ 9mm horizontal potentiometer (VR4) This filter consists of a 4.7Ω resistor with a ferrite bead over one of its leads, in series between the digital and analog +3.3V supplies, with a 1000µF filter capacitor for the analog supply. There is also a ferrite bead on the wire connecting the analog and digital grounds together. Software While the software to implement the delay function is not overly complex, there is still quite a bit going on. As usual, the source code will be available for download from the SILICON CHIP website (free for subscribers, or for a small fee). Most of the complexity resides in the “drivers” which must stream digital data between the microcontroller and CODEC and between the microcontroller’s internal RAM and the external SRAM chip. Circular buffering is used to allow for continuous recording and playback – for details, see the article on the SportSync Audio Delay Module (May 2011). Construction All the parts mount on a doublesided PCB coded 01110131 and measuring 148 x 80mm. This fits into a snap-together ABS plastic instrument case measuring 155 x 86 x 30mm. November 2013  41 22 µF 100nF 100nF IC1 1nF D2 100nF + 1nF PIC32MX470F 1 + 4004 100 µF 1000 µF + 100 µF 10 µF 100nF CON3 DC 7.5–12V 1k INPUT VR5 5k D1 4004 120Ω 200Ω 1k CON1 4004 10k 3.3Ω CON7 ICSP D3 100 µH 33pF REG1 LM317 5k VR6 100nF IC2 WM8731L 47k 47k 100Ω 100Ω OUTPUT 100 µF POWER 100nF L1 100nF 100nF 2x 1 µF 33pF S1 + + + 1000 µF CON2 100nF 100 µF + X1 100 µF K A 1 4.7Ω FB2 100 µF + 100nF 100 µF+ FB1 + 100nF 10k 01110131 Stereo Audio Delay/ DSP Board 24bit/96kHz 10k VR1 VR2 LED1 POWER IC3 R1LV0808ASB DELAY 2 DELAY 1 100nF VR4 1 µF 1 µF VR3 SILICON CHIP © 2013 NOTE: PARTS LABELLED IN RED ARE OPTIONAL – SEE TEXT Fig.4: follow this parts layout diagram to build the PCB, starting with the SMD ICs and the SMD capacitors. The parts labelled in red are optional. Install SRAM chip IC3 only if you need a delay that’s longer than 640ms and install VR2 (or VR4) if you want a dual channel delay unit with independently adjustable delays. Fig.4 shows the parts layout on the PCB. Don’t worry about the unpopulated pads; as stated above, they are there to accept extra circuitry to be described in the future. Start the assembly by fitting the SMD ICs. IC1 and IC2 are required while IC3 (the SRAM chip) is optional. They are each fitted in more or less the same manner, as described below. Note that IC1 and IC2 have very closely spaced pins (about 0.5mm apart) but if you are careful, it’s possible to hand solder these parts reliably. Begin by placing the IC to be installed alongside its pads and identify pin 1. In each case, there should be a small dot or depression in one corner (you may need to view the part under a magnifying lens and a strong light to spot it). This must line up with the dot and pin 1 marking on the overlay diagram and this should also be shown on the PCB silkscreen printing. Check that the part is the right way around, then apply a very small amount of solder to one of the corner pads. If you are right-handed, it’s easiest to start with the top pad on the righthand side. If you are left-handed, start with the top pad on the left side. Avoid getting any solder on the adjacent pad. That done, pick up the IC with a fine-tipped pair of angled tweezers 42  Silicon Chip and while heating the solder pad, gently slide it into place. Don’t take too long doing this; if you heat the pad too much it could lift so after a few seconds, if it isn’t in place, lift off and wait for the PCB to cool down before trying again. Once you have placed it, check the part’s alignment under a magnification lamp or similar. All the pins must be accurately centred over their respective pads. If they aren’t, don’t panic; it’s just a matter of re-melting the solder on that one joint and carefully nudging the IC in the right direction. You might get it right first time or it may take several attempts to get it in place, the goal being to eventually get it properly aligned without spreading solder onto any other pins or pads and without heating the PCB or IC enough to damage them. If you do get some solder on the adjacent pin, it’s still possible to adjust the position but you will now need to heat both pins to get it to move. Take care though, because if three or more pins end up with solder on them, you will likely need to remove the part, clean up the pads using solder wick and then start again. Once the part is in place, solder the diagonally opposite pin, then re-check the alignment under magnification as it may have moved slightly. If it has, you can reheat this second pad and gently twist the IC back into alignment. Once you’re happy, solder the rest of the pins but don’t worry too much about bridging them with solder (it’s almost impossible to avoid). Remember to refresh that first pin you soldered. Once all the pins have been soldered, spread a thin layer of flux paste along all the pins and gently press down on them with solder wick to suck up the excess solder. If done correctly, this will leave you with neatly soldered pins and no solder bridges. Go over all the pins once with the solder wick, then check under a magnifier for any remaining bridges. If there are any, add a dab of flux paste, then go back over them with the solder wick. Once that IC is in place, you can repeat the above procedure until all the SMD ICs have been fitted. By the way, rather than hand-solder these parts, you could use a home reflow oven (as described in SILICON CHIP magazine in March 2008). However, we realise that most constructors won’t have such a set-up and hand soldering is quite straightforward provided you follow the above procedure and have a good magnifying lamp and a fine-tipped soldering iron. Once all the ICs are in place, follow with the SMD ceramic capacitors, using a similar procedure; ie, add solder siliconchip.com.au +3.3V VR3 (ALT TO VR1) POT1 VR4 (ALT TO VR2) POT2 REPLACING VR1 & VR2 WITH VR3, VR4 Fig.5: potentiometers VR3 & VR4 can be installed instead of VR1 & VR2 if you want the delays to be externally adjustable (refer to the text for the various options). Don’t install both VR1 & VR3 or both VR2 & VR4. This photo shows the completed PCB without the optional SRAM chip (IC3) and with just VR1 fitted so that the unit functions as a basic stereo audio delay. Capacitor Codes Value 1μF 1nF 33pF µF Value IEC Code EIA Code 1.0µF   1u 105 0.001µF   1n 102   NA 33p   33 frustrating trying to re-align capacitors when this happens. Take care also not to short any IC pins when soldering in the SMD capacitors. They are located close to the ICs for performance reasons. Through-hole parts to one pad, then heat this solder and slide the part into place before soldering the other pad and refreshing the initial joint. Be careful not to get the SMD capacitors mixed up. In each case, wait about 10 seconds after soldering the first side of the capacitor before applying solder to the other side. This is necessary because the solder joint can remain molten for quite some time. If you try to solder the opposite pad too early, the capacitor will move out of alignment and it’s Proceed now with the low-profile components such as the resistors and diodes. Be sure to slip a ferrite bead (FB1) over one of the 4.7Ω resistor’s leads before soldering it in place. It’s best to check each resistor value with a DMM before fitting it as the colour bands can be difficult to read. The diodes are all the same type and all have their cathode bands facing to the top or righthand edge of the board. In the case of FB2, slip the bead over a resistor lead off-cut and then solder it to the board as shown in Fig.4. You can also mount axial inductor L1 at this time. Follow with REG1; bend its leads down about 6mm from its body, feed them through the PCB holes, fasten its tab to the PCB using an M3 x 6mm machine screw & nut and then solder and trim the leads. The horizontal trimpots can go in next, followed by the MKT and ceramic capacitors (disc and monolithic multilayer) and then pin header CON7 (not required if you have a preprogrammed microcontroller). That done, solder DC socket CON3 in place, followed by either VR1 or VR3 (to externally adjust the delay) but not both. In addition, you can optionally fit VR2 or VR4 (but not both). As mentioned earlier, if either VR2 or VR4 is fitted, the unit will operate as two separate mono delay channels. Now fit crystal X1 and the electrolytic capacitors, taking care to ensure that the latter are correctly orientated. Follow with power switch S1 and the blue power LED (LED1). This LED should have its leads bent at right angles 4mm from the base of the lens and then soldered so that the centre of the lens (and thus this short lead section) is 6.5mm above the top surface of the PCB. This aligns the centre of the LED Resistor Colour Codes o o o o o o o o o siliconchip.com.au No.   2   3   2   1   1   2   1   1 Value 47kΩ 10kΩ 1kΩ 200Ω 120Ω 100Ω 4.7Ω 3.3Ω 4-Band Code (1%) yellow violet orange brown brown black orange brown brown black red brown red black brown brown brown red brown brown brown black brown brown yellow violet gold brown orange orange gold brown 5-Band Code (1%) yellow violet black red brown brown black black red brown brown black black brown brown red black black black brown brown red black black brown brown black black black brown yellow violet black silver brown orange orange black silver brown November 2013  43 1 Audio Delay THD vs Frequency 13/09/13 15:33:36 0.5 0.2 THD+N % 0.1 0.05 0.02 0.01 0.005 0.002 0.001 20 50 100 200 500 1k 2k Frequency (Hz) with the centre of the switch. When bending the LED’s leads, pay attention to the “A” and “K” markings on the PCB as the longer (anode) lead must be soldered to the anode pad. You can accurately set the height of the LED by cutting a 6.5mm wide cardboard spacer and pushing the leads down onto this. The assembly can now be completed by soldering jack sockets CON1 and CON2 in place. Note that if you are using the type with six pins, you will also have to file or cut down the tall, rounded pieces of plastic just behind the screw threads (see photos), to prevent them from later fouling the case. Checking it out If you purchased a blank PIC32 chip, program it now (or purchase a programmed chip from the SILICON CHIP Online Shop). Complete kits will also come with a programmed chip. The circuit can be powered from a PICkit3 programmer at 3.3V. In fact, the whole unit will operate normally from this supply so you can test the 5k Fig.6: this graph shows that the delay unit should have little impact on sound quality, even when used with high-quality PA system (input signal level is 1V RMS). The ‘oscillation’ between 0.01% and 0.02% is due to the beat products of the 48kHz sampling rate and the input signal frequency (this is a form of aliasing). 10k 20k audio signal path immediately after programming the chip. If you don’t have a PICkit3, you will need to power the unit from a 7.5-12V DC plugpack. In this case, connect a voltmeter across the 3.3Ω resistor next to D1. Small alligator clip leads (or other test probe clips) are very useful for this purpose, as you can switch the unit on while watching the meter reading and switch it off immediately should the voltage across this resistor rise too high. Expect a reading in the range of 0.2-0.3V, depending on the exact resistor value and how you have configured the unit. Much less than 0.2V indicates that there is an open circuit somewhere while much more than 0.3V indicates a likely short circuit. If the reading is outside the expected range, switch off immediately and check for faults. The most likely faults would be one or more pins on an SMD chip bridged to an adjacent pin or not properly soldered to the PCB pad. Other possible faults include incorrect device orientation (primarily ICs, diodes and electrolytic capacitors) or poor/ bridged through-hole solder joints. Assuming all is OK, feed a line level audio signal into the input and connect the output to an amplifier. You should hear clear, undistorted audio with no delay. You can then adjust the delay pot setting(s) and check that this operates as expected. A fully clockwise setting will give a delay of either 640ms (no SRAM fitted) or 6s (SRAM fitted). If you know what signal level will be applied to the input when the unit is in use, you can adjust trimpots VR5 & VR6 to suit now. To do this, feed in a sinewave of the expected amplitude, then adjust these pots so that the outputs measure just under 1VAC. Any higher will lead to clipping and distortion. Ideally, you should calibrate them separately. If you aren’t sure of the input signal amplitude, you can wait until you get the unit “in the field” to set the level pots. One method is to turn them clockwise until clipping and distortion start, then back them off slightly. However, this does risk setting the level high enough for slight clipping to occur which may not always be obvious. If the input signal is under 1V RMS (0dBu = 0.775V RMS), then you can simply set them both fully clockwise. If all else fails, simply set VR5 & VR6 half-way. The unit can then handle input signals up to about 2V RMS but if the signal level is significantly lower than this, the noise and distortion will be less than optimal. Case preparation The front panel of the case needs holes for the power switch and LED, while the rear panel requires holes for the two jack sockets and the DC power plug. The front and rear panel artworks (Fig.7) can be used as drilling tem- SILICON CHIP www.siliconchip.com.au . AUDIO OUTPUT 44  Silicon Chip AUDIO INPUT www.siliconchip.com.au + STEREO AUDIO DELAY POWER Fig.7: these two artworks can be copied and used as drilling templates for the front & rear panels. They can also be downloaded as a PDF file from the SILICON CHIP website. 7.5-12V DC siliconchip.com.au The PCB is fastened into the case using four self-tapping screws which go into integral pillars. Note that the front & rear panels are normally fitted after the lid has been fitted. plates. These can also be downloaded from the SILICON CHIP website in a single PDF file (free for subscribers). It’s simply a matter of printing (or copying) the labels, then accurately taping them to the panels, drilling a pilot hole in the centre of each location indicated and then enlarging each to size using a tapered reamer. That done, remove the templates and de-burr the holes using a counter-sinking tool or oversize drill bit. Any adhesive residue can normally be cleaned up with methylated spirits. Check that the holes are large enough by test fitting the panels to the bare PCB. A new set of panel labels can then be printed onto photographic paper, attached to the panels using silicone adhesive and the holes cut out using a sharp hobby knife. The assembly can now be completed by screwing the PCB to the bottom of the case using four No.4 x 6mm selftapping screws, then placing the lid on top and snapping the front and rear panels on. If you have trouble fitting siliconchip.com.au the panels over the connectors, enlarge the offending holes slightly. Note that the DC power socket is recessed; most DC power plugs are long enough to fit through the rear panel. Using it All that’s left is to install the unit in its intended application and set the required delay. For PA systems, this can be a simple trial-and-error process whereby you incrementally increase the delay to get the best overall intelligibility at various points in the hall (or venue). A similar procedure will be required where the unit is used to provide two separate delays. Once adjusted, you can determine what the delay is actually set to by measuring either the frequency or the duty cycle at pins 4 & 5 of CON7. Even if the pin header is not fitted, you can simply “poke” probes into the plated PCB holes. A PWM signal is provided at each of these pins and its frequency in Hz is equal to the set delay in milliseconds (DC = no delay). The duty cycle varies from 0-99%, with 99% indicating maximum delay (ie, 0.64s or 6s, depending on whether IC3 is fitted). If the unit is set up for dual mono delays, measure pin 4 to determine the left channel delay and pin 5 the right channel delay. Note that the accuracy of these readings depends on the exact frequency of crystal X1. What’s coming That’s all there is for the delay function. In the next instalment, we’ll show you how to use the same hardware for echo or reverb. These functions are especially useful when used in conjunction with a microphone (for vocalists) or an electric guitar. As such, we’ll show you how to wire the unit up to a pedal, so that the effect can be switched on and off easily. We’ll also show you how to reconfigure the unit to run from a 5V supply, in case you want to power it from a computer SC USB port or similar. November 2013  45