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Using Cheap Asian Electronic Modules Part 16: by Jim Rowe
35MHz-4.4GHz digitally
controlled oscillator
This programmable frequency
module is based on the ADF4351 PLL
(Phase-Locked Loop) IC and it can
produce a sinewave from 35MHz to
4.4GHz, with crystal accuracy.
It can even be used as a sweep
generator and costs less than $30.
T
hat’s an impressive range of frequencies that can be produced by
this surprisingly compact (48 x 36.5
x 10mm) module. It is available from
various Chinese websites including
Banggood (siliconchip.com.au/link/
aajb) and AliExpress, as well as eBay,
for around $30.
It’s essentially a smaller, lower-cost
version of the ADF4351 development
board sold by Analog Devices. It runs
from 5V and has two RF outputs, one
180° out of phase with the other, allowing it to produce either single-ended
or differential signals.
It’s controlled using a serial bus
that’s connected via a 10-pin header,
which also makes connection to the
3.3V supply rail.
The ADF4351 chip at the heart of
the module is an advanced phaselocked loop (PLL) device. Before we
delve into how the ADF4351 works,
it’s a good idea to briefly cover the operation of PLLs.
Fig.1 shows the block diagram of a
basic PLL. It incorporates a negative
feedback loop, similar to the one used
to improve the performance of audio
amplifiers. But in this case, rather than
having a voltage divider providing the
feedback signal, we have a frequency
divider in the loop.
The PLL’s output signal (Fout) is
produced by the voltage-controlled
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oscillator (VCO) at upper right. The frequency
divider divides this output frequency
by a factor of N.
The resulting signal (Ffb) is then fed
to the negative input of phase detector PD, which compares its frequency
and phase with Fref, the signal from
a low-frequency reference oscillator,
fed to its positive input.
The PD output “error” pulses are fed
to charge pump CP, which uses them to
develop a fluctuating DC voltage with
a polarity and amplitude proportional
to the frequency/phase differences between Fref and Ffb. This voltage is then
low-pass filtered and used to control
the VCO’s frequency.
This feedback action causes the
VCO frequency (Fout) to stabilise at
very close to N times the reference
frequency, Fref. The PLL is then described as being “in lock”, since the
feedback action keeps Ffb locked to
Fref in both frequency and phase.
So even if Fref is fixed, by changing
the division ratio N, we can control
the frequency of Fout. Basic PLLs like
this have been in use for many decades
but more elaborate versions have also
been developed, to overcome some of
the limitations of a basic PLL.
One of these limitations is that the
minimum change in Fout is equal to
Fref, so you need quite a low reference
frequency to have fine control over the
output frequency.
But it’s easier to produce accurate
and stable reference oscillators at higher frequencies, so one of the first enhancements to PLLs was to add a reference frequency divider between the
Fref input and the phase detector PD.
Also, if the output frequency needs
to be up in the GHz (Gigahertz) range,
it’s not easy to provide a programmable
divider working at these frequencies.
So another early PLL improvement
was to add a fixed “prescaler” to the
feedback loop, between the VCO output and the input of the main (programmable) feedback divider.
Fig.1: block diagram of
a basic phase-locked
loop. They’re typically
used to generate a
stable high-frequency
signal from a fixed lowfrequency signal.
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Fig.2: block diagram of the ADF4351 wideband synthesiser IC. The integrated voltage-controlled oscillator has an output
frequency range of 2.2 to 4.4GHz, which, when combined with the RF divider, provides the ~35MHz to 4.4GHz range. The
fractional-N PLL controls the frequency from its three registers via the equation: Fout = Ffb × (INT + FRAC ÷ MOD).
Unfortunately, this reduces the output frequency adjustment resolution.
However, this can be overcome by
adopting what’s referred to as a “dual
modulus prescaler”.
This is essentially a prescaler with
a division ratio that can be switched
from one value (say P) to another (like
P+1) by an external control signal.
We don’t have space here to fully
explain the operation of modern (and
quite elaborate) PLLs but the prior description should be enough to understand how the ADF4351 works.
Inside the ADF4351
The block diagram of the ADF4351
IC (Fig.2) is somewhat more complex
than the basic PLL shown in Fig.1.
The VCO part of the device is labelled
“VCO CORE” and shaded pink.
There are actually four VCOs inside
the core, each used to generate a different frequency range. They are all tuned
by the dual varicap diode shown to its
right, using a tuning voltage fed in via
the Vtune pin.
Above the VCO core, you can see the
phase comparator and charge pump,
both blue. The charge pump output
goes to the CPout pin, so that an external low-pass filter can be used to
smooth the pulsating output of the
charge pump before it is fed back into
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the ADF4351 via the Vtune pin.
The differential outputs from the
bottom of the VCO core go to three
different destinations. One of these is
to the yellow “RF DIVIDER” block to
its right. This programmable frequency divider can divide the VCO output
frequency by 1 (ie, no division), 2, 4,
8, 16, 32 or 64.
This lets the chip generate low output frequencies while the VCO core is
operating at much higher frequencies
(2.2-4.4GHz).
The outputs from the RF divider
are fed directly to the chip’s main RF
output stage, which drives the A+ out
and A- out pins. The RF divider outputs also go to the inputs of two different multiplexers (digital selector
switches), shown in mauve.
The auxiliary multiplexer on the
right switches between the direct output lines from the VCO core and the
outputs from the RF divider and so
determines which is fed to the auxiliary RF output stage and then to the
B+ and B- output pins. The PDBRF
pin allows both RF output stages to be
disabled when they are not needed, to
save power.
The feedback (F/B) multiplexer at
left determines which of the same two
signal pairs go to the feedback divider,
in the yellow box. It’s also rather more
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complex than the simple feedback divider shown in Fig.1. That’s because
the ADF4351 offers the ability to implement either an integer-N or a fractional-N PLL, as required.
So the feedback divider needs three
registers which hold the integer division value, the fractional division
value and the modulus value, plus
control circuitry labelled “third-order
fractional interpolator”.
This circuitry effectively allows the
feedback frequency to be divided by a
rational number (fraction). The output
of this divider is then fed, via a buffer,
to the phase comparator.
The circuitry shown in the upperleft corner of Fig.2 takes the input
from the external reference oscillator
(fed into the REFin pin) and processes
it before feeding it to the other phase
comparator input.
As mentioned earlier, one of the refinements to earlier PLLs was to add a
reference signal frequency divider, so
that high-frequency reference oscillators could be used; hence the 10-bit
R counter.
But the ADF4351 also provides a
frequency doubler and an additional
divide-by-two stage for the reference
input, both of which can be switched
in or out under software control. This
gives the chip a great deal of flexibility.
May 2018 83
Fig.3: complete circuit diagram for
the ADF4351 frequency synthesiser
module.
The whole chip is controlled by
means of a simple 3-wire serial peripheral interface (SPI), shown at centre left of Fig.2.
Serial data from the PC or microcontroller is fed in via the DATA pin,
clocked into the serial data register and
function latch via clock pulses fed to
the CLK pin, and then latched into the
various control registers by feeding in
a pulse via the LE (latch enable) pin.
All functions of the ADF4351 chip
are configured using six 32-bit control
words, sent over this serial bus.
Multiplexer C and the other blocks at
the upper right of Fig.2 allow external
monitoring of the ADF4351’s status.
The “LOCK DETECT” block monitors the phase comparator and provides a high logic output on the LD pin
when the PLL is locked. Multiplexer
C allows either of the two phase comparator inputs or this lock status to be
fed to MUXout pin.
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The fast lock switch provides a signal which can be fed into the external low pass filter (between the CPout
and Vtune pins) when in “fast lock”
mode. So that covers the operation of
the IC itself.
The synthesiser module
The full circuit of the module is
shown in Fig.3 and most of the real
work is done by IC1.
All of the programming and status
monitoring signals to and from the
module are available at CON1. This
includes the DATA, CLK and LE lines
(ie, the serial bus) and also the CE (chip
enable), LD (lock detect), MUXout and
PDBRF (power down RF buffer) lines.
The reference signal is provided by a
25MHz crystal oscillator (XO), shown
at upper left, with its output fed to the
REFin pin of IC1 via a loading/coupling
circuit comprising two 1nF capacitors
and a 51W resistor.
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Note that there is also provision for
feeding in a different reference signal,
via the SMA socket labelled MCLK. In
order to do this, you’d need to remove
the 0W resistor connected to pin 3 of
the onboard XO. If you are using the
onboard XO, the MCLK socket can be
used to monitor its output via a scope
or frequency counter.
The resistors and capacitors connecting the CPout and SW pins of IC1
(pins 7 and 5) to the Vtune pin (pin 20)
form the low-pass loop feedback filter.
The RF output signals from the
RFOA+ and RFOA- pins (12 and 13)
are taken to the RFout+ and RFoutSMA sockets via matching/filtering
circuits using L2, L3, L5 and L6, plus
two 1nF capacitors.
Notice that the output pins are fed
with the +3.3V supply voltage via L2
and L3. In this module, the auxiliary
RF outputs RFob+ and RFob- (pins 14
and 15) are not wired up.
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Fig.4: when connecting the ADF4351 synthesiser module to an Arduino-based device, a few extra resistors are needed.
These resistors form a voltage divider, as the module can only handle 3.3V signals, while the Arduino’s outputs have a
swing of 5V. Note the changes needed if using a V2 module at the end of this article.
The whole module operates from a
3.3V supply, derived from the 5V input at CON2 via REG1, an ASM1117
low-dropout regulator. This AVdd rail
powers all of the analog/RF circuitry
directly.
The digital supply rail, DVdd, is derived from AVdd using LC filters comprising inductors L4 and L1 and a
number of bypass capacitors.
There are two indicator LEDs. LED1
is connected between the DVdd line and
ground and indicates when the module
has power while LED2 is connected to
the LD (lock detect) pin of IC1 (pin 25)
and indicates when the PLL is in lock.
All the remaining components are
for bypassing and stability, apart from
fuse F1 and diode D1, which prevent
damage in the event that the 5V power source is connected with reversed
polarity.
Controlling it with an Arduino
I initially hooked the module up to
an Arduino Uno using the simple circuit shown in Fig.4. The three main
control lines MOSI, SCK and LE are
not taken directly to the DAT, CLK and
LE pins of the module but instead via
1.5kW/3kW voltage dividers.
This is because the inputs of the
ADF4351 can only cope with 3.3V
signals, whereas the Arduino outputs
have a 5V output swing.
The LD signal fed back from the
module to the Arduino’s D2 pin does
not need a divider because it’s going
the other way and the Arduino inputs
function well with a signal having a
swing of 3.3V.
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Note also that Fig.4 indicates that
the 5V supply for the module can come
from either a plugpack or from the 5V
output of the Arduino. I adapted an
Arduino sketch I found on the internet, written by French radio amateur
Alain Fort F1CJN (siliconchip.com.
au/link/aaje).
Mr Fort’s sketch was written for an
Arduino with an LCD button shield
but I decided to adapt it so that it
would work with the simple configuration shown in Fig.4, relying on the
Arduino IDE’s Serial Monitor to send
commands to the ADF4351 and to indicate the PLL’s output frequency and
whether it was locked or not.
I also connected one of the PLL
module’s RF outputs to my frequency counter, via a prescaler, so I could
monitor it.
The results were quite impressive. I
could type in any frequency between
35MHz and 4.4GHz, with a resolution
of 0.01MHz (10kHz) and the module’s
output would lock to that frequency
in the blink of an eye.
I also monitored the current drawn
by the module and found that it varied
between 110mA and 145mA, depending on the output frequency.
I also checked the accuracy of the
module’s 25MHz on-board reference
XO and found it to be 25.0000734MHz
or only 73.4Hz high. Since this equates
to an error of just +2.936ppm, it seems
quite accurate.
So that’s one easy way to get the
ADF4351 module going with an
Arduino. The sketch (“ADF4351_and_
Arduino_SC_version.ino”) is available for download from the Silicon
Chip website.
Driving it from a Micromite
I also hooked the module up to a
Micromite LCD BackPack combination and wrote some code so that
it could be controlled via the LCD
touchscreen.
The circuit is shown in Fig.5 and it’s
about as simple as you can get. In this
The bottom view of
this module is shown
at approximately
twice actual size.
The bottom
of the board
is populated
by five 10kW
10kW
pulldown resistors
for the breakout pin
connections.
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May 2018 85
Fig.5: when connecting the ADF4351 module to a Micromite no extra
components are needed, unlike with an Arduino. However, the newer version of
the module requires a 10kW resistor between CE and +3.3V.
case, no resistive dividers are needed
on the SCK, MOSI and LE lines because the Micromite’s logic pins have
a swing of 3.3V.
I used a “software” SPI port rather
than the hardware one used by the
Micromite to communicate with the
LCD and touchscreen, to prevent possible interaction.
The embedded C code (CFUNCTION) needed to provide this added
port is included in the MMBasic program I wrote for this approach. Software SPI port performance is limited
but that isn’t a problem as the amount
of data to transfer is small.
A USB charger was used to supply
5V to the ADF4351 module because
its current drain is a little too high for
the BackPack to provide.
The software uses just two screens,
as shown below. The initial screen (at
left) displays the current frequency
and gives you the option of touching
the button at the bottom if you want
to change it.
You will then get the second screen,
which allows you to key in a new frequency, displayed below the current
frequency.
When you’re happy with the new
figure, simply touch the OK button
and the module jumps to the new
frequency. The program returns to
the main screen, displaying the new
frequency.
So for those who would like to team
up the module with a Micromite, this
program (“Simple ADF4351 driver
program.bas”) should get you off to a
good start. Like the Arduino sketch,
it’s available from the Silicon Chip
website.
Performance
I checked the module’s RF output
performance at quite a few different
frequencies, using my Signal Hound
USB-SA44B spectrum analyser controlled by Signal Hound’s “Spike”
software.
The results were quite impressive,
as you can see from the two spectrum
plots. One plot shows the output at
275MHz, with the only significant
spurs visible being at ±50MHz with
an amplitude of -57dBm.
The other plot shows the output at
4.200GHz, with two spurs again visible but this time both on the low side:
one at 4.150GHz (far left) with an amplitude of about -53dBm and the oth-
The sample program running on a Micromite LCD BackPack. These are the only two screens the software uses, one to
enter a specific frequency for the module to output and another to display the current frequency.
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Spectrum analysis of the ADF4351 module’s output performance at 275MHz (left) and 4.2GHz (right). The RF output
performance over the full range was good, with only a few visible spurs outside the programmed frequency. These
normally correspond to beat frequencies or integer-multiples of the reference and oscillator frequency.
er at 4.175GHz with an amplitude of
-61dBm.
In both cases, the amplitude of the
main output carrier is very close to
0dBm. This turned out to be the case
over most of the range, in fact.
The only region where the carrier
level did drop (to around -20dBm) was
in the vicinity of 2.45GHz – perhaps by
design, to minimise interference with
WiFi and Bluetooth systems.
Overall, the ADF4351 frequency
synthesiser module is very impressive,
especially when you consider its frequency range and price.
It could even be used to make your
own VHF/UHF signal and sweep generator, teamed up with a Micromite
and a 4GHz digital attenuator module
that we will describe in next month’s
issue.
These changes will be critical to
successfully connect the module to
a micro, so here are the main details
listed below:
1. Many of the connections to the
10-way pin header (CON1) have
changed, as shown in Fig.6.
2. There is now no on-board pullup
resistor connecting IC1’s CE pin to
the +3.3V (DVdd) line, nor are there
pulldown resistors connected between the CLK, DATA and LE pins
and ground.
To ensure normal operation of the
module with either an Arduino or a
Micromite, an external 10kW resistor
must be connected between the CE
and +3.3V pins of CON1.
To ensure maximum stability, it’s
a good idea to also connect an external 10kW resistors between the LE pin
and ground.
Once the above changes are made,
version 2 of the module performs just
as well as the earlier version.
Useful links
The module from AliExpress: www.
aliexpress.com/item//32848807357.
html
The module from eBay: www.ebay.
com.au/itm/142521016834
ADF4351 data sheet: siliconchip.
com.au/link/aajc
Fundamentals of PLLs: siliconchip.
SC
com.au/link/aajd
Fig.6: CON1 has been
changed completely on
the newer version of
the ADF4351 module.
Every signal, except
for CLK, is connected
to a different pin
location.
A new version of the
ADF4351 synthesiser module
Just recently we received a second
ADF4351 Synthesiser module and
discovered that it was a “V2” module
which had been changed in a number of ways compared with the first
version.
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May 2018 87
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