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A 5-year design odyssey: The CS448 1kV isolated 4-channel oscilloscope If you open up a piece of modern test equipment, such as a spectrum analyser or oscilloscope, you will be amazed at the sheer number of components, the intricacy of the layout and the huge amount of work which must have gone into its design. Here’s a rare glimpse into the challenges which Bart Schroeder, of Cleverscope, had to overcome in designing their latest product, a USB ’scope with particularly strict performance requirements. He tells the story in his own words . . . W people will find it interesting and enlightening. ay back in September 2011, I was at the ElectroneX show in Melbourne demonstrating our Determining the requirements CS328A two-channel, 100MHz USB scope. Rather The key specifications we came up with for the scope, than resting on my laurels, I started to plan our next product. based on the requirement for working with a VSD, were: This would be a four-channel scope with each channel • A ±800V range, adequate for probing circuits like moproviding 1kV isolation from the others, and from the host tor speed controllers which are powered from rectified PC. Having isolated channels makes a scope much more three-phase mains. versatile since it frees you up to probe voltages across any • 1 part in ±8000 resolution (1 part in 16000). This requires component in a circuit. This is especially useful when worka 14-bit analog-to-digital converter (ADC; 214 = 16384) ing on motor speed controllers, especially variable-speed with very low noise. The result will be a voltage resodrives (VSD) – see the panel below for details. lution of 0.1V on the ±800V range. Less than two LSB As well as adding two channels and providing the iso(least significant bits) RMS noise would be good, giving lation, the new scope would also have significantly better a usable resolution of 0.2V – just enough for accurately resolution and bandwidth than our then-current models. measuring the current through floating low-value shunts. It would be by far our best offering. • Less than 1% error when measuring the current through a I had no idea at the time that it would take so long to low-value sense resistor with achieve this! I was finally able a 1x probe while slewing over to reveal our new high-perfora 680V range (ie, full-wave mance CS448 PC-based scope The Cleverscope CS448 is most definitely NOT rectified mains). at PCIM in Nuremberg, Ger• An input capacitance many in July 2017. a ’scope you would find on many workbenches. ×10pF to limit common mode It has been a learning expeIndeed, its price alone (more than $13,000 capacitively-coupled current rience for me and I have a lot plus options!) would strongly suggest that. to a tolerable level. more grey hair than I did five However, for engineers, design labs, QC/QA years ago. ADC selection departments and other “high end” users it In this article, I will describe The first question was the journey from idea to finwould be very high on their “wish list”. where to put the ADC; on ished product and some of The Cleverscope CS448 is right up there with the isolated side, or the nonthe pitfalls that I encountered other “professional” scopes; – there aren’t isolated side. The noise floor along the way. I want to share sets the dynamic range and is the story since I think many many that can beat it at anything like the price! WHO’S IT INTENDED FOR? 68 Silicon Chip Australia’s electronics magazine siliconchip.com.au Inside the CS448 (shown here about 2/3 life size). Of particular note is the extensive shielding and the fibre optic links. The five symmetrical transformers transmit power to the isolated inputs and signal generator. related to the number of components between the input and the ADC. A reduced component count means lower noise and since low noise was a requirement, that meant that the ADC needed to be on the isolated (ie, input) side. We already determined that our ADC needed a resolution of at least 14 bits. And it would help for it to be a lowpower device because we have to get its power across the isolation gap. We would also need a method for sending the digitised signal to the non-isolated side. The only realistic transfer method is via an optically isolated serial bus and the only standard method that allows synchronization (which is important in a multi-channel scope) is JESD204B, a standard for ADC and DAC data transfer. The scope also incorporates a signal generator and digital input. Multiple units can be linked together. siliconchip.com.au Australia’s electronics magazine October 2018  69 Variable Speed Drives and H-bridges The idea for the CS448 Isolated Channel Oscilloscope came to me when I was designing Variable Speed Drives (VSDs) for electronic motor speed control. A VSD uses three halfbridges to generate a three-phase signal to control the rotation of a three-phase motor. SILICON CHIP has published a three-phase VSD design in the past, the Induction Motor Speed Controller from the April and May 2012 issues (later updated in the December 2012 and August 2013 issues). It uses an integrated threephase bridge containing six IGBTs (insulated gate bipolar transistors, a BJT/Mosfet hybrid device), drivers and controlling circuitry. You can also use two half bridges to control a stepper motor or permanent magnet DC motor. This is called a full bridge or H-bridge. Each half-bridge uses two transistors to switch one side of the load between a negative and positive supply voltage. The half-bridge is sometimes known as a “totem pole” arrangement, as the two transistors are stacked between the supply rails. Fig.1 shows a full bridge circuit built using Mosfets and half-bridge gate driver ICs, which switches the voltage across Zload. Normally, one end of Zload is connected to +VBUS and the other end, to -VBUS. When Q1 and Q4 are switched on (and Q2 and Q3 off), current flows from +VBUS to -VBUS through the path indicated by the solid grey line, with the red probe giving a reading near +VBUS and the blue probe near -VBUS. In contrast, when Q2 and Q3 are switched on (and Q1 and Q4 off), current flows through the path indicated by the dashed grey line, with the red probe reading near -VBUS and the blue probe near +VBUS. In other words, current flows through Zload in the opposite direction in this case. If you alternate between these two conditions rapidly, the inductance of Zload (which is normally a motor coil) causes the current to increase or decrease more slowly and so by controlling the percentage of time spent in each state (using pulse width modulation [PWM]), you can vary the voltage across Zload smoothly. The voltage is normally made to vary in a sinusoidal manner, with a frequency determined by the desired motor rotation speed. Design challenges That all sounds pretty nice and neat but in the real world, designing a good bridge circuit and controlling it properly is not that easy. For example, when switching between the two states, you need to make sure that you never have both Q1 and Q2 on at the same time, or else current will “shoot through” them from +VBUS to -VBUS and they will heat up and possibly fail. The same applies for Q3 and Q4. But at the same time, you want to transition between the two states as rapidly as possible for maximum efficiency. So you really need to tune the Mosfet gate drive to suit the particular devices. You have to keep in mind the gate charge and discharge times as well as the Mosfet switch-on and switch-off times (which are all different and can vary between samples of the same device). And with the high voltages, currents and fast slew rates, you have all sorts of other factors such as parasitic capacitance within the Mosfets and between tracks and compo70 Silicon Chip Fig.1: a typical H-bridge driver. Because the load is “floating”, using a traditional ’scope will not give useful readings . . . and might let the smoke escape! nents, which cause induced voltages to appear in places where you may not necessarily expect them. The bottom line is that when you are developing this type of motor drive, you really need to be able to observe its behaviour and that means monitoring the gate drive waveforms, the voltage across the motor winding(s) and the current through each device. And once you have done this with a dummy load, you also need to test with a real motor – this is known as functional testing. You have to make allowances for temperature, component variation and drift. All this is virtually impossible if you can’t use an oscilloscope to measure the signals at various points in the circuit and make sure they are correct and match your design calculations. The ground reference bugbear But, and it’s a big but, in circuits like this, many of the signals you are interested in are not ground referenced Unfortunately, most scopes have ground-reference inputs. Look at the purple and green probes in Fig.1, which are measuring the gate drive for high-side Mosfets Q1 and Q3. These voltages are relative to the sources of those FETs, at the red and blue probes, which are switching rapidly between -VBUS and +VBUS. You could “float the scope” by powering it from an isolating transformer but that only gives you one floating channel, and besides, it’s dangerous, and there might be quite a high capacitance or inductance to ground through the power supply, which would cause very high currents to flow through the probes, possibly causing damage. FETs (including GaN and SiC varieties) can switch in 10100ns. If the switching time is 10ns, with 100pF capacitance and a 680V bus, you’ll get 6.8A (CV÷dt = 100pF x 680V ÷ 10ns)! So you really need a low capacitance to Earth. The traditional way to overcome these limitations is to use a differential probe but even a good one will have a poor Common Mode Rejection Ratio (CMRR) at high frequencies. As an example, the Tektronix P5200A has a CMRR of 30dB at 3.2MHz. 3.2MHz equates to a rise time of tr 100ns (1÷Δf). Lots of modern transistors switch faster than that. Australia’s electronics magazine siliconchip.com.au If you had a 680V bus (as is typical for three-phase power supplies), the probe will generate a spurious signal equal to 680V <at> -30dB = 0.032 x 680V or 21.8V That’s a larger magnitude than the signal you’re actually trying to probe so it will obliterate it! Why measure the gate drive you say? After blowing up quite a few IGBT modules, I can tell you that the gate drive has to be right. Adequate signal resolution It’s also important to ensure that there was not too much power loss in the transistors. Running the motor and having the switching devices blow up is not the best way to test this! A better way is to measure the voltage across the transistor while measuring the current through it and multiply to get power. Referring to Fig.2, this means that you need to measure VDS across the transistors as well as the voltage across the drain resistors, which is a proxy for the current through the transistor. These resistors are typically low value (1-10mΩ) types. VDS will transition between the saturation voltage, say 0.23V and the off state voltage, say 680V. So you really need a resolution of 0.1V, or one part in 6800, to measure this accurately. Your average scope has an 8-bit ADC, giving one part in 256 resolution. Assuming that the input range is close to 680V, the resolution will be 2.6V and noise will mean that the actual practical resolution is at least 5V. That’s not very useful. So to really see what is going on in this H-bridge, we need an isolated scope with good CMRR at high frequencies and high enough resolution to do 1 part in 6800. If you now look at the target specifications for the CS448 scope at the start of this article, you will see that they are all based on the requirements of working with this type of circuit. Having said that, this is far from the only situation in which you will need these capabilities. Many circuits have sections that are floating or which have different local grounds, and high-side shunts are quite common. A scope with isolated channels is very helpful in these cases. And a good CMRR, high resolution and low noise are all desirable attributes no matter what you are probing. After a search, we settled on the Intersil ISLA214S50 ADC, a 500Msps 14-bit ADC which could transfer all the samples over two serial lanes, at 4.375 Gbps per lane (using data compression). The ADC needs a buffer/amplifier in front of it and the best part we could find for this job was the Analog Devices ADA4817, a 1GHz bandwidth FET-input op amp. This has just 4nV÷√Hz voltage noise, low distortion and a good slew rate. We matched this with the ADA4937 differential ADC driver, with only 5.8nV÷√Hz output noise, 1.9GHz bandwidth and -102dB (<0.001%) distortion. We talked to Analog Devices and discovered that the ADA4817 included an input analog multiplexer, so the plan was to have two ranges and use the multiplexer to switch between them to keep everything as simple as possible. We’d make the ranges ±800mV and ±8V. With these two ranges, we could use a 10:1 probe to get ±8V or ±80V with full bandwidth and the ±800mV range would work well with current sense resistors, giving a 100µV resolution. A 100:1 probe would give us a ±800V range and some combination of these probes would cover just about every situation. Isolation We did a market search looking for the best way to transmit the two serial data streams to the FPGA (field-programmable gate away) that would be used to control all the scope functions. Eventually, we found an English company, Advanced Fibreoptic Engineering, who could make us pairs of optically isolated transmitters and receivers with a holder and fibre links between them. We paired these with the Texas Instruments ONET4291VA transmitter driver and limiting amplifier receiver. It sounds simple but it wasn’t! Clock generation We wanted all four channels to use the same clock source so that they would be perfectly synchronised but that would have meant another fibre channel and anyway, the jitter on a fibre channel is way too high for precise timing. In effect, our 14-bit ADC would become an 8-bit ADC. So we settled on using a programmable clock oscillator (the Silabs Si598) as the low-jitter clock source. The idea was that we could measure the channel frequency from the serial data coming back and adjust the clocks to make them all the same. Power supply and other details Fig.2: high side gate drive waveforms – the parasitic effects are the big deal! siliconchip.com.au As we said above, a low capacitance between the channel common (- input) and the real system ground is absolutely critical. This capacitance is determined by the power transformer inter-winding capacitance and the capacitance between the channel components/tracks and the chassis, plus the capacitance of the scope probe to the surrounding environment. We can control the power transformer and the channel placement. We decided to use a Maxim MAX13256 H-bridge driver to provide the isolated supplies for each channel with the companion Halo TGMR-501V6LF lowcapacitance (10pF) capacitor as specified in their literature. The transformer chosen was UL/EN60950 approved, which we needed. Australia’s electronics magazine October 2018  71 Fig 3: clock jitter reduces the usable resolution of the ADC. The jitter from our clock generator is very low and does not adversely affect ADC performance. We decided to use a cheap-as-chips STM8 8-bit microcontroller for channel control, communicating via an optoisolated serial link with the system FPGA. Most scopes offer 1MΩ and 50Ω input impedances, so we put in a relay in each channel to switch in the 50Ω. You need a relay to switch the 50Ω resistor in and out, to ensure low parasitic impedance and capacitance. We knew we’d need shielding to stop noise from all those high-frequency FPGA signals from getting into the sensitive analog front end. So we design a U-shaped shield with fingers which could be pushed down through slots in the board, to make a shield right around the board. This would mate with a ground plane on the main board that the digitiser would be plugged into. Building a prototype We put a lot of time and effort into designing and building a prototype, only to find that it a lot of problems! But I guess you only find problems by building something and then you have to learn from that and revise your design. The problems we found included: • The ADA4817 has bugs in it – the multiplexer did not work as specified and when the device was disabled, it dragged the inputs to -5V instead of the inputs going high-impedance. I was able to contact the designer of the chip at Analog Devices and they confirmed our findings. That means that our two-range design was unusable. • The MAX13256 H-bridge driver and transformer generated large common mode transients on the isolated ground which added to any signal being measured. Our power supply design was simply not suitable • The relay and 50Ω load resistor could not be turned off fast enough when the 1kV maximum input voltage was applied, with the resistor and relay disappearing in a puff of smoke. We had to abandon a 50Ω input impedance option. (Users could still connect a 50Ω terminator to the input if you really needed it, with the responsibility for possibly blowing it up being with them!) • The Si598 clock generator output drifted at the rate of about 15Hz/second, which meant that long duration captures would not have inter-channel synchronisation after 60 milliseconds or so. It also meant our intent to do Frequency Response Analysis (FRA) would fail. We needed a better clocking system. 72 Silicon Chip Fig 4: common mode rejection ratio is below -115dBc all the way to 65MHz in the unit being tested here. This is way better than just about any differential probe you’re likely to come across – even those costing many thousands of dollars. And a differential probe only gives you a single isolated channel – this scope has four! • The ISLA214S50 ADC lost gain/offset alignment between the two internal ADC’s used to achieve 500MSPS and became horribly non-linear if the signal exceeded the input range by even 1mV. This meant that we could not use the ADA4937 differential amplifier because input overloading is very common when a user is looking at a portion of a signal. We needed to add components to limit the input signal, to keep it within the ADC’s specified range • The shielding was good for stopping noise but useless for achieving a good CMRR. Because the shield was referred to the system earth, any capacitance between components on the board and the shield injected current into the front end circuit, polluting the measured signal. We needed a better shield design. • We had different RC time constants between the AC and DC paths in our two ranges. These generated slowly rising or falling pulse responses when using 10:1 probes. Of these problems, the power supply was the most serious and hardest to fix. Making an isolated supply that injects only microvolts into the system being measured became one of the most difficult challenges of the whole design. Coming up with a better design In the end, we went through three major versions of the scope, with two tweaks to the last version, before we were 100% happy with the performance. The power supply took a year to completely sort out. The main lesson learned during this process was that it was absolutely vital to keep everything symmetrical! You need a very symmetrical power switch, controlled equal slew rates on the power switch edges and a symmetrical power transformer (see photo of main PCB). The transformer needs to be balanced and centre-tapped with minimal inter-winding capacitance. Our final design has two very widely separated winding with a very low capacitance between them. The windings are wound bifilar so that each half of the winding is symmetrical to the other. The clock system also needed a considerable amount of work. The only way to have all the clocks synchronised was to have a common clock. This meant that we had to use the FPGA as a clock master and distribute that clock to all the channels. This approach means we can also synchronise more than one scope together, effectively turning Australia’s electronics magazine siliconchip.com.au ADA4817 At left is the original input PCB which looked good on paper but had a number of shortcomings which we had to address. The final version of the board ADA4817 is shown at right – there’s a lot more performance 50 OHM packed into RELAY this one! shows the Murata FOTs and the interconnecting optic fibre. You can also see the 1kV isolation gap and the isolation power transformer. Shielding STM8 ADA4937 Si5344 STM8 ISLA214S50 Si598 ONET4291VA ONET4291VA POWER TRANSFORMER AC/DC SWITCH POWER TRANSFORMER The shielding is absolutely crucial to getting a good common-mode rejection ratio (CMRR); in other words, to preADA4817 vent changes in the channel ground relative to Earth from showing up in the differential signal. LMH6553 The key is that the common-mode current (due to the channel capacitance, as described earlier) must flow along the outside of the shield to the common point, which is ISLA214S50 the centre tap of the isolation transformer. From there, it flows through the transformer inter-winding capacitance to the case. The shield goes right around the PCB and is soldered to the BNC socket shields. It incorporates a heatsink for the ADC and clock generator chips. The plastic cover is to provide the required 1kV isolation. FIBRE FIBRE ONET4291PA (2x under) FOT two 4-channel scopes into one 8-channel scope. So we needed another optic fibre isolated channel between the FPGA and each input channel to carry the clock signal, which is a 100kHz square wave generated by the FPGA. This is then fed to an SiLabs Si5344 PLL/jitter attenuator and multiplied by a factor of 5000, resulting in a 500MHz clock for the ADC. The Si5344 is a truly magical device; its output has a jitter of below 0.1ps. That is good enough for an 85dB signal-to-noise ratio when sampling at 100MHz, which is more than the ADCs are capable of, so it does not compromise its performance (see Fig.4). The Si5334 output is precisely in-phase with the 100kHz master clock, meaning all four channels (and any downstream units) are properly synchronised. Range switching and isolation While the multiplexer in the ADA4817 does not work, the part is otherwise very good and so we decided to keep it. That meant that we needed a new scheme to switch input ranges. We ended up doing this using RF photomos switches, which are a similar to optocouplers (the two white packages). We used a clamping LMH6553 differential ADC driver to avoid saturating the ADC, solving the problems mentioned above, and we got rid of the 50Ω option since there was no way to make it failsafe. We determined that our two-way fibre isolator was now limiting the performance of the scope. Murata in Japan came to the rescue with Fibre Optic Transceivers (FOTs) and interconnect fibre. These dual-channel, bidirectional 10Gbps units have only 60ps edge uncertainty variation between units. This meant that we could do a good job of synchronizing our 2ns clock periods; our final system achieves ±160ps phase variation between channels. The adjacent photo siliconchip.com.au The end result The final design is shown in the photo at left. It’s always good to end with something which works well, especially after putting in so much effort. Fig.4 shows the measured CMRR for Channel D of the CS448 scope with serial number EQ10019. It’s above 110dB right up to 65MHz! There are slight variations from unit to unit but they all exceed 100dB up to 65MHz. 110dB down from 680V is 2mV. With a 10:1 probe, that means you have a useful resolution of about 20mV, which is more than good enough for examining floating gate voltage signals, as we shall demonstrate below. Alternatively, if you are using a 1:1 probe to measure the voltage across a current sense resistor, given the typical 1% accuracy, that means you can measure around 200mV fullscale, which equates to 100A through a 2mΩ shunt. That sounds pretty useful to me. Now for some real measurements demonstrating just how handy the CS448 scope is. Fig.2 shows a direct measurement of two Mosfet high-side gate drives, where the common (bridge output) is slewing 500V in 8ns, as shown at the bottom of the plot on page 71. We can clearly see the Miller plateau (where the gate voltage stops rising as the gate charges up) on Gate 1 (orange trace) and the droop caused by the parasitic capacitive voltage divider formed by the Mosfet’s inherent gatedrain and gate-source capacitances, through which current flows as the Mosfet switches on, affecting the drain-source voltage as the switch goes high. Similarly, on Gate 2 (green trace), we see a pulse caused by the capacitive divider as the corresponding output (blue trace) goes low. We have never seen plots of actual gate measurements as detailed and accurate as these for such a high-voltage bridge slewing so quickly. Many such measurements that you see are swamped by noise and commonmode signals. Conclusion It was a lot of work but I am very pleased with the performance of the new scope. You can get more information about the Cleverscope CS448 from the company’s website at: https://cleverscope.com/products/CS448 SC Australia’s electronics magazine October 2018  73