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For almost forty years now, CMOS has been the technology of choice for implementing digital logic. And over that time, transistors have consistently shrunk, allowing higher logic density, faster operation and lower power consumption. But further improvements are becoming increasingly challenging. Quantum-dot Cellular Automata technology could provide a quantum leap (no pun intended) in logic performance. V irtually all digital chips these days are built using Complementary Metal Oxide Semiconductor (CMOS) technology. This is a mature technology, with many advanced fabrication facilities worldwide churning out large numbers of high-performance microprocessors. But it is becoming increasingly difficult to improve this technology. To gain better performance, CPU fabrication processes need to achieve faster switching speeds, lower leakage currents, higher density, lower power consumption (and thus heat generation) and all this while keeping reliability high and costs low. Quantum-dot Cellular Automata (QCA) is one of the most likely technologies to succeed CMOS. Other possibilities which are currently being investigated include the Single Electron Transistor (SET) and Carbon NanoTube Field Effect Transistor (CNTFET). QCA is an emerging concept in computational nanotechnology. QCA cells can be used to perform all complex computational functions essential for general-purpose computation. This includes the majority function (the output value is the mode of the input values, ie, if more than half the cells are logic high than the output will be a logic high), inversion (an input of 1 becomes an output of 0, and vice versa) and fan-out (the output of one cell feeding multiple inputs). QCA technology may replace CMOS technology in the near future because it can be fabricated with tiny cells (on the nanometre scale) which can provide high density, and it offers the possibility of high operational speeds – into the terahertz range! It also has ultra-low power consumption, without any leakage currents at the nanoscale level. The biggest challenge at the moment is finding suitable QCA chip fabrication techniques which can be implemented on an industrial scale. This article describes the basic principles of using QCA technology to implement logic functions in an integrated circuit. Basics of QCA technology The QCA cell is the fundamental component in QCA technology. It comprises four quantum dots which are connected through electron tunnel junctions – see Fig.1(a). There are four places where electrons can conform inside the cell, but only two electrons are trapped inside. These electrons will take residence in the two locations which require minimum energy (ie, place the cell in its lowest stable energy state), for example, as shown in Fig.1(b). To be in a low energy state, the two electrons must be at the furthest possible distance apart, which means that they will reside in opposite corners of the cell. Coulomb interaction between electrons in adjacent cells (in this case repulsion) is used to gain the necessary computing logic states like logic zero and logic one. The two possible states are shown in Fig.1(c), and they are arbitrarily assigned to represent zero and one. The logic state passes from one cell to another nearby due to the electric field interactions of the electrons in the wells. Cell polarisation propagates through all nearby cells and continues all over the circuit until it reaches the end. By Dr Sankit Ramkrishna Kassa, SNDT Women’s University, Mumbai, India Image source: https://softologyblog.wordpress.com/2016/11/17/more-experiments-with-coupled-cellular-automata/ 78 Silicon Chip Australia’s electronics magazine siliconchip.com.au Because of these interactions, no current flows between the cells; the electrons only move within the cell, and as they move in opposite directions, their magnetic fields cancel out (as do their electric fields, except at very short distances from the cell). Therefore, very little power is consumed by QCA circuits when transitioning from one logic state to another. Fig.2 shows the structure of a QCA wire, used to pass information. The cells are simply arranged side-byside. Right-angle turns are possible, and logic signals can be distributed by T-intersections (fan-out) or even X-intersections. The resting state of each cell in the wire is the same (one or zero) because electrons repel each other, as they are negatively charged, and this allows the electrons to remain as far apart as possible. As mentioned above, this is the lowest stable energy state. One end of the wire is actively driven, either from an external signal or by another QCA cell which is being held in a particular state, and the signal propagates along the wires as each cell moves into its lowest energy state, ie, aligned with the other cells. Propagation speed and direction are controlled by choosing which cells are on which clock phase, which is explained later in more detail. Fig.3(a) shows how a logic inverter can be formed from QCA cells. Essentially, it’s just two wires which meet at one corner. Once again, the electrons re-arrange themselves to be as far apart as possible, but in this case, that happens when the logic values in the output wire are the opposite of those in the input wire. Note that it’s easier for us to show cells diagonally opposite each other, but in reality, there would probably be a slight overlap to enhance the electric field interactions of the electrons in the corners. Note also that the actual fabricated cells will not necessarily be square; if they have rounded or cut-off corners, that would allow the electrons to be closer again. The inverter shown in Fig.3(b) works in the same manner, but because the input wire splits, its electrons can be in proximity to two corners of the first cell in the output wire, doubling the interaction between them and making the result both faster and more reliable. siliconchip.com.au Fig.1: a quantum cell consists of two electrons located in four possible wells, joined by four tunnel junctions. The electrons tend to reside in diagonally opposite wells as this is the lowest energy state. The two resulting possible states are defined as logic one and zero. Fig.2: the logic state propagates along a QCA wire consisting of several cells placed side-by-side, due to the repulsion of the electrons in adjacent cells. They will stabilise at the greatest distance possible, which is where all cells are either in the zero or one state. Fig.3: an inverter is formed by placing two QCA wires in contact at their corners. The lowest energy state in this configuration is with all the cells in one wire in one state, and the cells in the other wire in the opposite state. This can be doubled-up to make a more robust but functionally equivalent inverter. Fig.4: for QCA wires to cross, multiple layers are needed, allowing cells to be vertically stacked. A cell above or below will take on the opposite polarisation (ie, it acts as an inverter) but it’s simple to arrange for double inversion so that the cells at either end have the same polarisation, as shown here. Cells can also be stacked vertically, to form 3D structures, so that wires can cross. Fig.4 is an orthographic projection of two wires crossing, with different logic polarisations. Note that each QCA cell stacked vertically above another effectively forms an inverter. But so long as the number of inverters in Australia’s electronics magazine each wire is even, the states at either end will be consistent. Building logic with QCA cells The most fundamental structure in QCA logic is the three-input majority gate, shown in Fig.5(a). All other logic structures such as AND gates, OR August 2019  79 Fig.5: the 3-input majority is the most fundamental logic gate used in QCA logic. This shows two possible implementations of the gate, functionally identical but with the inputs and outputs arranged differently. Any of the four surrounding cells can be the output; this is determined by which cell is free to change state (ie, is not actively driven) and the three inputs are interchangeable. gates, XOR gates, adders, multiplexers etc are usually formed from this arrangement. Once again, it works because the cells settle in the lowest possible energy state. When all three input cells have the same state (all zero or all one), the middle cell aligns with the others, and thus so does the output – and the polarity of all the cells becomes the same. But when one of the input cells is in a different state from the other two, its effect on the state of the middle cell is weaker, as the electric field acting on the middle cell is the combination of the three external fields. And since the electrons can only exist within the wells (based on quantum theory), they will settle in the wells which are on average furthest from the others nearby. Therefore, when two of the inputs are one and one is zero, the middle cell and the output are one, and when two of the inputs are zero and one is one, the middle cell and output settle at zero. Hence, we get our ‘majority out of three’ effect. Given that the structure is symmetrical, how do we determine which cells are the inputs (which are functionally interchangeable) and which is the output? It merely depends on which cells are being actively driven. The three inputs are driven externally or from the ‘outputs’ of other wires/structures, while the output cell is free to take on either state, and can then go on to influence other cells. The arrangement shown in Fig.5(b) has the same effect as that of Fig.5(a), working on the same principle, except that the electrons interact in the corners rather than along the edges of the cells. There are some logic structures where this configuration would fit better. Note that the middle cell’s polarisation is opposite to that shown in Fig.5(a), but this is re-inverted at the output, so is of no consequence. 80 Silicon Chip Forming the usual logic gates Other logic implementations Fig.6(a) shows how an OR logic gate is formed from a 3-input majority gate, by changing one of the three input cells to a cell which has its value fixed at one. This would generally be built using a normal cell, but having an external electric field (eg, from a nearby conductor held at a particular potential) which forces it to remain in this particular state permanently. It might also be built by doping the cell in such a way that it only has two wells. So now, we have the situation where we only need one of the two inputs to be a one before the majority of inputs are one, and thus the output is one – which is, in effect, the OR function. In other words, the output is one unless both input values are zero. The AND gate shown in Fig.6(b) is made in the same way, except now the fixed cell has a value of zero. So for the output to be one, both inputs must have a value of one. Building an XOR gate is a little more complicated. Fig.7 shows how three AND gates, an OR gate and an inverter (to turn the AND gate into a NAND gate) can be configured to form the XOR function. And Fig.6(c) shows this same structure implemented using QCA. You should be able to identify the AND gates, OR gates and inverter by comparing sections of Fig.6(c) with Figs.6(a) & (b) and Fig.3(a). But in case it isn’t clear, we’ve labelled the gates for you, and colour-coded the cells. External inputs are shaded green, outputs blue, inverters red, fixed gates grey and 3-input majority gates orange. Any logic structure can be built up from AND, OR and XOR gates, although with QCA, it’s often easier to return to ‘first principles’ and use 3-input majority gates as the primary element, as this results in smaller and faster designs. Because QCA cells interact by the electrons contained within repelling electrons in other cells, it is possible to design more complex QCA gates by taking advantage of the fact that cells not directly adjacent can still have some interactions. In the designs described above, the interactions between adjacent cells dominate, and so cells further away have no real effect, except perhaps to slightly speed up or slow down the expected transitions. But say you have a cell with two adjacent cells, and those two cells are in opposite states, ie, one is zero and one is one. Their electric fields would cancel out around the cell in question, so you would not know what state it would settle in. However, that may then be determined by the next closest set of cells. It is possible to take advantage of this to produce more compact implementations of certain sets of logic. For example, Fig.6(d) shows an alternative XOR gate design. As you can see, it is much more compact than the ‘obvious’ design shown in Fig.6(c). The cells shaded in pink are synched to clock one, while those in yellow are tied to clock two (see below for an explanation of clocks). When the inputs are both zero or both one, you can follow the flow of logic through the gate using the rules described above and you get the right answer at the output (ie, zero in both cases). However, it’s not so straightforward when one input is zero and the other is one. In this case, the cell to the left of the output has a zero cell at one corner and a one cell at the other corner. So its state will depend on the states of cells further to the left. One disadvantage of this approach is that this logic block may need to be clocked more slowly than the one shown in Fig.6(c) because it relies on a weaker interaction (the fixed cell Australia’s electronics magazine siliconchip.com.au Fig.6: the 3-input majority gate is combined with cells that have fixed polarisation to form an AND or OR gate. The combination of three AND gates, one OR gate and an inverter forms an XOR gate. interacting being the tie-breaker two cells away), and will take longer to settle into a steady state. On the other hand, it requires fewer clock phases from input to output, which could mitigate the slower clock requirement. But until QCA logic is implemented successfully on an industrial scale, we won’t know whether that speed impact negates the other advantages of such a configuration. There are many other possible XOR gate implementations and one of the other options may possess the best trade-off between size, delay and clock speed. All QCA circuits require a clock which most importantly provides power to run the circuit, as well as synchronisation and control over the information flow through QCA wires. QCA logic normally uses four clocks, and each clock has four phases 90° apart. Each of the four clocks are 90° out of phase from the prior clock. This is known as Landauer clocking. The four phases are switch, hold, release and relax, as shown in Fig.9. The designer can choose which clock feeds which cell, and therefore, in which directions signals flow through the cells. During the switch phase, the QCA cells settle down to one of the two defined logic states, as influenced by its neighbours, some of which will normally be in the hold phase. During the hold phase, the QCA cells maintain their current state. During the release and relax phases, the QCA cells become unpolarised in preparation for the next switch phase. Often, several adjacent cells run on the same clock, forming small static ‘islands’ through which information can propagate freely during the switch phase. Their states are locked together during the hold phase. Fig.7: this shows how the XOR gate operates, based on other gates which are easier to build. Fig.8: three 3-input majority gates plus two inverters can be used to build a onebit adder with carry inputs and outputs. These can be easily combined to form multi-bit adders (eg, 16-bit, 32-bit or 64-bit). Clocking siliconchip.com.au Australia’s electronics magazine The clock phase relationship of cells is often shown through colour-coding, although we have avoided this in most of the earlier diagrams, as it can be confusing to beginners. However, choosing the right clock phase for each cell is very important, as depending on the design, changing a cell from one clock to another one can stop it from working properly. Note the number of cells allowed on one clock must be <= eEk ÷ (KB × T). Where Ek is the kink energy, KB the Boltzmann constant and T is the operating temperature in Kelvins. The kink energy is the difference in energy between two cells with the same polarity and the opposite polarity. A one-bit adder To demonstrate building a more complicated (and indeed useful) logic block using QCA, we will now show how a one-bit adder can be formed. These can be daisy-chained to allow August 2019  81 Fig.9: QCA logic uses a four-phase clock. During the switch phase, cells start unpolarised and begin to polarise while the tunnelling barrier is raised. In the hold phase, the barrier is raised high enough so that tunnelling cannot occur and the cell is locked to its current polarisation. In the release phase, the barrier is lowered and the cell returns to its unpolarised state. In the relax state, the cell remains unpolarised and thus is in a neutral or “ground” state (neither “0” or “1”). This neutral state is sometimes shown as a electron located in a fifth well in the middle of the four outer wells. Fig.10: a practical implementation of the one-bit adder using QCA cells. You can see how the three majority cells correspond to Fig.8 by the A/B/C labelling. One problem with this adder that the A input is located inside the circuit. Also note that due to the way it is clocked, the series of cells that come from the B majority actually skips over the cell in the intersection. This is because when the cell marked “X” is in the hold phase, therefore polarised, the green cell directly below it will be in the release phase (unpolarised) and have no effect on the blue cell below. This means that during the switching phase, the blue cell will primarily be affected by cell X two cells above it. 82 Silicon Chip Australia’s electronics magazine larger numbers to be added. For example, 32 one-bit adders form a single 32-bit adder, capable of summing two integers between 0 and 4,294,967,296 (ie, a little over four billion), or between -2,147,483,648 and +2,147,483,647. That isn’t to say that using 32 onebit adders is necessarily the best way to add two 32-bit numbers, but it will undoubtedly give you the right result. The basic concept of how to form a one-bit adder using QCA is shown in Fig.8, along with its truth table. “A” and “B” are the two numbers to add up (either zero or one), and “CARRY IN” is the carry output of the previous stage, which is usually fixed to zero for the first stage. The result is a two-bit number, represented as “SUM OUT” (the lower bit) and “CARRY OUT” (the upper bit). As you can see, the one-bit adder function can be formed from three 3-input majority gates (labelled “MV” for “majority vote”) and two inverters, shown as circles at two of the gate inputs. One possible QCA implementation of this logic configuration is shown in Fig.10. The colour coding this time shows the clock phases for each cell. One critical part of this circuit is the placement of the clocks as it helps control the flow of logic. Note that the distance between outputs, inputs and computational cells is critical, due to unintended interations between cells if they are moved to slightly different positions. Therefore, designing QCA logic is a bit more tricky than implied by our description so far, and assigning clock phases correctly to cells each cell is also vital, giving them time to stabilise in the correct polarity. It's also important to avoid having too many or too few cells on the same clock, depending on the clock timings that will be used. One potential problem with this circuit is the location of one of the inputs, as it is surrounded by the circuitry. This means multiple layers would be required to provide input data. This makes it more difficult to expand to form a multi-bit adder, however, this example circuit is much simpler than other arrangements. If you follow the signal flow, represented by the small black arrows, you will see that this arrangement calculates the logic exactly as shown in Fig.8. The cell states are shown for siliconchip.com.au Fig.11: input, output and clock waveforms for the one-bit adder as simulated by QCADesigner. Shown from top-to-bottom are inputs A, B and the Carry Input, then the Carry and Sum Output followed by Clocks 1-4. Note that the Carry Output is on Clock 1 so it appears 90° earlier than the Sum Ouput on Clock 2. Note that the output for the first values of the simulation are not always accurate. Ain Bin Cin Cout Sum Clk1 Clk2 Clk3 Clk4 the case where A=1, B=0 and CARRY INPUT=1, giving the correct result of SUM OUTPUT=0 and CARRY OUTPUT=1. Fig.11 shows the simulated waveforms from the one-bit adder shown in Fig.10, once the four clocks have been applied as required for each cell. Note how the outputs swing between ±1V, but are close to 0V during the release and relax phases. The outputs should be sampled during the hold phase to ensure valid data is received. The QCADesigner tool If you would like to try your hand at designing QCA-based logic, you can try out QCADesigner. This is a free, open-source tool which is available online at: https://waluslab.ece.ubc.ca/ qcadesigner/ It facilitates design, layout and simulation of QCA circuits. The user can quickly lay out a QCA design with an extensive set of CAD tools. Several simulation engines allow rapid and accurate simulation. This tool has been used by researchers to design full adders, barrel shifters, random-access memory, etc. Editor’s Note: sometimes simulation using QCADesigner can be inconsistent. We’ve found that the first and last values will differ between runs on some circuits and are best ignored. QCA chip manufacturing There are four types of fabrication siliconchip.com.au classes defined for QCA IC manufacturing: semiconductor, molecular, metal-island and magnetic. a) Semiconductor: the existing, highly advanced CMOS manufacturing technology can be used to fabricate QCA cells. Cell polarization is encoded as charge position, and quantumdot interactions rely on electrostatic coupling. But with current CMOS technology, only small numbers of cells can be fabricated at a nano-scale level. b) Molecular: a fabrication method to build QCA cells from single molecules. Its advantages include: highly symmetric QCA cell structure, very high switching speeds, extremely high device density, operation at room temperature, and even the possibility of mass-producing devices using selfassembly. c) Metal-island: the first technology that has been used to demonstrated QCA operation in the real world. Quantum dots are built using aluminium with metal islands as big as 1 micrometre in dimension. The problem with this is that the cells are too large to be truly competitive with CMOS. For that, QCA needs to reach the nano-scale level. Also, metal islands that large require extremely low temperature for correct operation. d) Magnetic: also referred to as MQCA, is the latest trend in QCA fabrication. Here, the interaction between magnetic nanoparticles provides the Australia’s electronics magazine two polarities. The magnetisation vector of these nanoparticles is analogous to the polarization vector in all other implementations. In MQCA, the term ‘quantum’ refers to the quantum-mechanical nature of magnetic exchange interactions and not to electron-tunnelling effects. Devices fabricated this way can operate at room temperature. Conclusion If nano-scale QCA-based ICs can be mass produced, it will have a huge impact worldwide and completely change the electronics industry. Powerful chips will become tiny and operate at extremely high speed with very low power consumption. This will have an especially big impact on the following industries: military, security, communications, gaming, artificial intelligence, autonomous vehicles and chip design. The power needs are projected to be so low that QCA devices will be able to power themselves using solar cells integral to the chips. More information The links below should explain QCA in greater detail: siliconchip.com.au/link/aaqg siliconchip.com.au/link/aaqh siliconchip.com.au/link/aaqi siliconchip.com.au/link/aaqj siliconchip.com.au/link/aaqk siliconchip.com.au/link/aaql SC August 2019  83