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Follow-up By DR Sankit Ramkrishna Kassa, SNDT Women's University, Mumbai, India We introduced QCA technology in the August 2019 issue (siliconchip. com.au/Article/11774) as a possible future alternative to CMOS digital logic. It could possibly operate much faster than traditional logic and at a much smaller scale, but has not yet been made to work in commercial processes. This article investigates a more energy-efficient approach to QCA than the traditional 3-input majority gate structure. A s described in the previous article, Quantum-dot Cellular Automata (QCA) is an emerging nanotechnologybased approach for designing and implementing electronic circuits. The aim is to beat the well-developed Complementary Metal Oxide Semiconductor (CMOS) technology. QCA has the possibility of running at exceptionally fast speeds (in the terahertz range – 1000GHz plus!), at smaller sizes and with extremely low power consumption (in the picowatts). The two basic gates used in QCA logic are the inverter and the 3-input majority gate. Any digital circuit can be designed using these two gates. The majority voting function can be written in Boolean logic as M(A,B,C) = AB + BC + AC. This article describes a new style of 3-input majority gate (MG) struc- Fig.1: a comparison of the ‘standard’ QCA 3-input majority gate (a), the novel one described here (b), along with its truth table (c). siliconchip.com.au ture, which is analysed with the help of mathematical modelling. Fig.1(a) shows the standard 3-input majority gate, while Fig.1(b) shows the proposed new structure. Fig.1(c) is the truth table for both gates (they are logically equivalent). The main advantage of the new structure is that it gives the designer the flexibility to move all of the cells utilised by a certain amount. Fig.2: here’s how a two-input AND gate (a) or OR gate (b) can be formed from a single 3-input majority gate. Note that the fixed input (zero or one, shown in grey) can be any of the three. It’s up to the logic designer, and depends on the best routing for the other signals. Also note that the whole thing can be rotated or flipped to suit the design. Australia’s electronics magazine February 2021  25 Fig.3: the QCADesigner software simulation output for the AND and OR gates shown in Figs.2(a) & (b). By comparing the A, B & Y values, you can see that they provide the expected functions. This means that, when incorporated into a larger logic structure, it is possible to minimise the area used by the overall design. This also can lead to increased speed and lower power consumption. Two-input AND gates and two-input OR gates can be implemented easily using the proposed 3-input majority gate, as shown in Figs.2(a) & (b). General operating principles We won’t go back over all the operating principles of QCA in detail as they were explained in the August 2019 article. But as a refresher, each cell has four wells, and two electrons are trapped within. They can rest in two possible positions, with the electrons in diagonally opposite wells. The electric fields of the electrons in adjacent cells influence the resting position of any given cell. The electrons tend to rest in the lowest potential energy position. When cells are organised in rows, the positions of the electrons are identical in all cells (in one of the two possible states). This is because the electrons posses the same negative charge, and therefore weakly repel each other. So the system of QCA cells tends towards a stable position unless held in place by an external ‘power’ source. The potential energies for each cell are calculated via the formula for electrostatic potential energy of a point Table 1: full adder design comparison Proposed design QCA cells Area (µm2) Clock cycles 1 57 0.06 [1] 59 0.07 1 Reported design [2] 61 0.08 0.75 Reported design [3] 71 0.08 1.5 [4] 79 0.08 1.25 Reported design [5] 93 0.09 1 Reported design Reported design 26 Silicon Chip charge in the presence of another point charge. More detail on this topic can be found at: siliconchip.com.au/ Shop/6/5652 By taking advantage of the way that adjacent cells interact, we can design various functions, including the aforementioned 3-input majority function and the AND and OR gates. It is also possible to build 5-input majority gates, and even larger structures, which save space and time compared to using multiple 3-input majority gates. Full adder design Fig.4 shows a ‘full adder’ designed using this new gate style. A full adder takes two binary digits (zero or one) [1] Abedi D, Jaberipur G, Sangsefidi M (2015) Coplanar Full adder in Quantum-Dot Cellular Automata via Clock-Zone Based Crossover, IEEE Transactions on Nanotechnology 14: 497 - 504 [2] Angizi S, Alkaldy E, Bagherzadeh N, Navi K (2014) Novel Robust Single Layer Wire Crossing Approach for Exclusive OR Sum of Products Logic Design with Quantum-Dot Cellular Automata, Journal of Low Power Electronics 10: 259–271 [3] Hashemi S, Navi K (2015) A Novel Robust QCA Full-adder, in 5th International Biennial Conference on Ultrafine Grained and Nanostructured Materials, Procedia Materials Science 11: 376 – 380. [4] Hashemi S, Tehrani M, Navi K (2012) An efficient quantum-dot cellular automata full adder, Scientific Research and Essays 7: 177-189. [5] Zhang R, Walus K, Wang W, Jullien G (2005) Performance comparison of quantum-dot cellular automata adders Circuits and Systems, IEEE Int. Symp. Circuits Syst. 3: 2522-2526 Australia’s electronics magazine siliconchip.com.au Fig.4: a full one-bit adder (three bits input, two bits output) built using the novel 3-input majority gate along with a 5-input majority gate and some ‘free’ inverters (made by lining up the cells corner-to-corner). The inputs are cyan and the outputs are mauve, with the other colours indicating the quadrature clock domain on which each cell’s transitions are timed. Each path from input to output has four transitions (green, purple, yellow to red), as the adder takes one full clock cycle to operate. Fig.5: the equivalent logic diagram for Fig.4, along with its truth table. Fig.6: using QCADesigner to simulate the design shown in Fig.4 confirms that it operates as expected. Compare the Carry and S0 outputs here to the truth table in Fig.5. plus a ‘carry’ bit (also zero or one) and adds all three to produce a number between zero and three (two-bit binary values of 00 and 11 respectively). Fig.5 shows the logic functions used to implement this full adder while Fig.6 shows the result of simulating this adder using QCADesigner. Adders are widely used within digital ICs, so this is a very practical demonstration. Note the 3-input majority structure at the left of Fig.4, which is identical to that shown in Fig.1(b). Table 1 shows a comparison of this full adder design to previously reported designs. This shows that it is superior in terms of cell count and area occupied to all the previously reported designs, and as fast or faster than most of them. Note that almost all of these designs could be improved by modifying them to incorporate this new gate structure, reducing their occupied area and power consumption. SC siliconchip.com.au Australia’s electronics magazine February 2021  27