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IC Fabrication Image Source: GlobalFoundries Inc. from inception to cutting-edge technology Last month, we covered the invention and history of integrated circuits (ICs) and the manufacturing process. Now we pick up where we left off, discussing how transistor counts keep increasing and feature sizes get smaller, culminating in the cutting-edge EUV technology. Part 2 – shrinking nodes, EUV, components – By Dr David Maddison T he technology generation in the semiconductor industry is referred to as a ‘technology node’ or a ‘process node’. It is a length measurement referring to the shortest transistor gate that could be fabricated with that particular technology node. But that has not been the case since about 1997, according to https://en.wikichip.org/ wiki/technology_node At about the 45nm technology node (around 2007), Intel used gate lengths 14 Silicon Chip of 25nm and no smaller, as undesirable results occurred otherwise. With the introduction of the 22nm process in late 2011, Intel fundamentally changed the design of the transistor with the introduction of the fin field-effect transistor (FinFET). This provided a higher transistor density without having to shrink the gate size. Thus, the feature size somewhat lost its meaning. Confusingly, today the technology Australia's electronics magazine node referred to is more a marketing term for new or improved fabrication processes with no specific relation to any physical feature size. However, the International Technology Roadmap for Semiconductors (ITRS) traditionally described the technology node in relation to the halfpitch between the smallest spacing of two metal conductors that could be made with a given fabrication process (see Fig.24). siliconchip.com.au The following process nodes are currently in use, depending upon a manufacturer’s capabilities and the devices being fabricated: 180nm, 130nm, 90nm, 65nm, 45/40nm, 32/28nm, 22/20nm, 16/14nm, 10nm, 8/7nm, 5nm. At present, only Samsung, TSMC (Taiwan Semiconductor Manufacturing Company) and Intel can use the three smallest nodes. Table 1 shows when each node was introduced. Microprocessor transistor count A common measure of the complexity of a CPU (central processing unit) or GPU (graphics processing unit) is the transistor count on the die. The transistors are usually Mosfets. The highest transistor counts currently for a variety of integrated circuits are shown in Table 2. The V-NAND (Vertical NOT-AND) flash memory chip, also known as 3D NAND by Samsung, is a 3D chip with 2000 billion transistors. This high transistor count is achieved by using many layers in the memory “stacks”. For example, a 128Gib V-NAND chip has 24 layers, and V-NAND chips with up to 160 layers are under development. 500+ layers are anticipated in the future. In 2019, Samsung had a 1024GB flash chip made from eight stacked 96-layer V-NAND chips; hence the huge transistor count – see Fig.25. We will discuss 3D chips further in the final article in this series. The Cerebras Systems Wafer Scale Engine 2 (WSE-2), designed for artificial intelligence, is the largest chip ever built, both by transistor count and physical size – see Fig.27. It contains 2.6 trillion transistors, 850,000 processor cores, has 40GB of on-chip memory, uses the 7nm technology node by TSMC and has an area of 46,225mm2 – that’s massive! A typical high-end processor is a bit larger than a postage stamp, around 1/100th that area. Moore’s Law The increase in IC component density with time has been observed to scale according to “Moore’s Law”. It is not a physical law but an observation reflecting improvements in technology and manufacturing processes. Gordon Moore was one of the founders of Fairchild Semiconductor. In 1965, Moore observed that the number of components on an integrated circuit siliconchip.com.au Fig.24: the traditional method by which technology nodes are named, according to the ITRS. Original source: https:// en.wikichip.org/wiki/ File:tech_node.svg (CC BY 3.0) Fig.25: how 3D NAND flash memory works, as distinct from 2D NAND. Original source: Wikimedia user NVMdurance Table 1 – process node introduction year Node Year Model 10µm 1971 Intel 4004 6µm 1973 Toshiba TLCS-12 3µm 1976 Intel 8085 1.5µm 1982 Intel 80286 1µm 1985 Intel 80386 800nm 1988 Cypress CY7C601 | Motorola 68030 (1987)? 600nm 1992 PowerPC 601 350nm 1995 Intel Pentium P54CQS 250nm 1997 Intel Pentium Katmai 180nm 1999 Intel Pentium III (Coppermine) 130nm 2001 Fujitsu SPARC64 V 90nm 2004 PowerPC 970FX 65nm 2006 Intel Pentium 4 Cedar Mill 45nm 2007 Panasonic UniPhier 32nm 2009 Intel Sandy Bridge (2nd-gen Core) 22nm 2011 Intel Ivy Bridge (3rd-gen Core) 14nm 2012 Samsung FinFET 14LPE 10nm 2016 Samsung 10LPE | TSMC 10FF 7nm 2018 TSMC N7 5nm 2019 Samsung 5LPE 3nm 2022 (estimate) 2nm 2024 (estimate) The years are mostly estimates for when nodes were first produced (we have primarily focused on microprocessors rather than including other ICs such as DRAM). Outlier examples include RCA’s CD4000 series which may have started 10μm production before Intel’s 4004; there’s also the Intel 1103 which was an 8μm process in 1970. Australia's electronics magazine July 2022  15 Table 2 – highest present transistor counts for various ICs Year IC type Model # of transistors 2020 AI processor Cerebras Wafer Scale Engine 2 2.6 trillion 2019 Flash memory Samsung V-NAND 2 trillion 2022 Processor Apple M1 Ultra 114 billion 2020 AI/deep learning Colossus Mk2 GC200 59.4 billion 2020 GPU 59 billion Alderbaran MI250X Table 3 – CPU transistor count over time was doubling every year. In 1975, he predicted that the number of components would double every two years – see Table 3. The second version of the law stayed true until around 2010, when a slowdown in the component count increase was observed. There is now a doubling approximately every two and a half years – see the full-page plot overleaf. Ultimately, there is a physical limit beyond which component density cannot increase. So improvements will have to come through better computing algorithms and different electronic architectures, such as optical computers or neural networks based on the structure of the human brain (Fig.26). Year Model Transistor count Node Area 1971 Intel 4004 2250 10μm 12mm2 1974 Motorola 6800 4100 6μm 16mm2 1974 Intel 8080 6000 6μm 20mm2 1975 MOS Tech. 6502 4528 8μm 21mm2 1979 Zilog Z8000 17,500 4μm(?) 35mm2(?) 1979 Intel 8088 29,000 3μm 33mm2 Silicon wafer size 1979 Motorola 68000 68,000 3.5μm 44mm2 Table 4 shows the evolution of standard silicon wafer size over the years (also see Figs.28 & 29). The larger the wafer, the more ICs can be made in one pass, so the more economical and cheaper the manufacturing process becomes, at least to a point. Standards have been established for 450mm wafers (see the “Global 450 Consortium (G450C) Program” at https://f450c.org/infographic/). But there is resistance to the uptake of that size due to the massive investment in new equipment and the questionable economics of using this size. It will probably be eventually adopted, though. 1982 Intel 80286 134,000 1.5μm 49mm2 1989 Intel 80486 1,180,235 1μm 173mm2 1993 Intel Pentium 3,100,000 800nm 294mm2 1998 Intel Pentium II 7,500,000 250nm 113mm2 1999 Intel Pentium III 9,500,000 250nm 128mm2 2000 Intel Pentium 4 42,000,000 180nm 217mm2 2003 AMD K8 105,900,000 130nm 193mm2 2006 Intel Pentium D 362,000,000 65nm 162mm2 2008 Intel Core i7 731,000,000 45nm 263mm2 2010 IBM POWER7 1,200,000,000 45nm 567mm2 2013 IBM POWER8 4,200,000,000 22nm 650mm2 2013 Xbox One (AMD) 5,000,000,000 28nm 363mm2 2015 Oracle SPARC M7 10,000,000,000 20nm 400mm2(?) 2018 Apple A12X 10,000,000,000 7nm 122mm2 2019 AMD EPYC Rome 39,540,000,000 7nm + 12nm 1008mm2 2021 Apple M1 Max 57,000,000,000 5nm ~432mm2 2022 Apple M1 Ultra 114,000,000,000 5nm ~864mm2 Table 4 – largest silicon wafer diameter by year Year Diameter Typical thickness 10×10mm dies per wafer 1960 25mm ? 2 1963 28mm ? 3 1969 50mm 275μm 9 1972 75mm 375μm 29 1976 100mm 525μm 56 1981 125mm 625μm 95 1983 150mm 675μm 144 1992 200mm 725μm 269 2002 300mm 775μm 640 Proposed 450mm 925μm 1490 Future 675mm >1mm(?) 3427 16 Silicon Chip Australia's electronics magazine Wavelength of light for lithography Over time, as the number of transistors on a chip has increased, lithography has required shorter and shorter wavelengths of light to produce the smaller IC feature sizes. According to the major equipment supplier, ASML (siliconchip.au/link/ abdu), their light sources changed over time as follows: • Early lithography systems used mercury lamps to produce blue light with a wavelength of 436nm, enabling feature sizes of 1000nm (1μm). • UV light sources with a wavelength of 365nm allowed feature sizes of 220nm. • KrF excimer laser light sources with a wavelength of 248nm allowed feature sizes of 80nm. • ArF excimer lasers with a wavelength of 193nm allowed feature sizes of 38nm. siliconchip.com.au Fig.27: the monster Cerebras Systems Wafer Scale Engine 2 (WSE-2) chip, the world’s largest integrated circuit both by physical size and transistor count. Fig.26: one possible way to improve performance beyond Moore’s Law and the physical limitations of semiconductors is using “neuromorphic” architecture to emulate the human brain but implemented in silicon. This is DANNA: Dynamic Adaptive Neural Network Arrays, a 2D grid representing neurons or synapses of the brain with programmable connectivity between them. Source: University of Tennessee (http://neuromorphic.eecs.utk.edu/ pages/research-overview/) • Extreme UV (EUV) uses light at 13.5nm, allowing feature sizes of around 3-7.5nm. Extreme UV lithography Traditionally, every new technology node decreased lineal feature dimensions by 30%, thus reducing IC area by 50% and power consumption also dropped correspondingly. This is known as Dennard or Mosfet Scaling. But this process has been slowing since around 2006, and the increase in transistor density has also not kept up with Moore’s law. As described last month, optical lithography has been moving to smaller wavelengths in the drive to smaller feature sizes. The most advanced commercially-­ made chips use extreme ultraviolet (EUV) lithography. Currently, only one company based in Veldhoven in the Netherlands can make the required machines: ASML (www.asml.com/ en/). It took them 10 years and US$25 billion to develop EUV machines, and siliconchip.com.au they charge up to US$200 million per machine. Despite this, there is a waiting list to purchase them. ASML has sold about 140 EUV machines in the last ten years. This machine is so advanced that it is regarded as strategically sensitive – see siliconchip.au/link/abdw These are among the most complicated machines ever manufactured. Quoting from the article at siliconchip. au/link/abdy: • One EUV system contains 100,000 parts and weighs approximately 180 tonnes. • An EUV system ships in 40 freight containers, spread over 20 trucks and three cargo planes. • The mirrors used in EUV systems are so flat that if one were to be blown up to the size of Germany, the biggest bump would be less than 1mm high. • An EUV system controls beams of light so accurately that it is equivalent to shining a torch from the Earth and hitting a 20 cent coin on the moon. Australia's electronics magazine Fig.28: 2-inch (51mm), 4-inch (100mm), 6-inch (150mm), and 8-inch (200mm) silicon wafers after they have been ‘diffused’. Each die visible on their surfaces will become a separate device once the wafer is sliced up. (GNU Free Documentation License) Fig.29: an Intel 300mm wafer with VLSI (very large scale integration) circuits fabricated onto it. The next phase would be testing; then, it would be cut up into individual dies (chips), ready for packaging. Source: Wikimedia user FxJ (public domain) July 2022  17 18 Silicon Chip Australia's electronics magazine siliconchip.com.au Fig.30: this plot shows that “Moore’s Law”, the prediction that the IC transistor count would double roughly every 18 months, was prescient. Source: https://ourworldindata.org/ uploads/2020/11/Transistor-Count-over-time.png (Max Roser, Hannah Ritchie, CC BY 4.0) Computers were once people! Integrated circuit manufacturer business models IC fabrication facilities or foundries are incredibly expensive to build and operate and must be kept running at maximum capacity to pay their bills. This is one of the reasons why some companies specialise in design while others provide fabrication services only. Some companies, known as integrated device manufacturers (IDMs), both design and manufacture devices. Examples of such companies are IBM, Intel, NEC, Samsung and Texas Instruments. Other ‘fabless’ (and possibly also fabulous) companies only design devices and get others to manufacture them. Examples include AMD (since 2008, when they sold their fab to GlobalFoundries), Apple, ARM, Broadcom, Marvell, MediaTek, Nvidia, Qualcomm and Xilinx. “Pure play” companies only manufacture devices that fabless companies design. Examples of pure play foundries include GlobalFoundries (headquartered in New York with fabs in various locations including Germany, Singapore, United States), TSMC (Taiwan) and UMC (Taiwan). The term “computer” was coined by English poet Richard Brathwaite (1588-1673), who published a book in 1613 called “Yong Mans Gleanings”. He used it to refer to a person who makes calculations. He wrote: I haue read the truest computer of Times, and the best Arithmetician that euer breathed, and he reduceth thy dayes into a short number: The daies of Man are threescore and ten. The unique mirrors in the EUV system are made of silicon and molybdenum, and are among the flattest in the world. Of course, a foundry needs more than just EUV machines. They need about 200 different large-scale machines, and the workflow through these has to be precisely coordinated. A vast number of supplies, processes and personnel work together to form a huge operation. ASML started as a subsidiary of Philips in 1984. Christophe Fouquet, its Executive Vice President, said that their first lithography machine “looked like a projector”. ASML is more valuable than some of its customers, such as Intel. They have come a long way from those early days. Only five chipmakers can afford to buy the most advanced machines. Its customers include Intel, Samsung and TSMC, who combined provided more than 84% of its business in 2021. There are thousands of chip foundries worldwide, so most cannot make the most advanced chips. The TWINSCAN NXE3600D is ASML’s most advanced EUV lithographic system and supports volume production at the 5nm and 3nm nodes for both logic and DRAM. It uses extreme UV of 13.5nm wavelength and can expose 160 300mm wafers per hour, with a maximum exposure field of 26mm x 33mm (see Fig.31). To produce the EUV light, a CO2 laser is fired into droplets of tin that vaporise and emit EUV light. The UV wavelength of 13.5nm is almost in the X-ray range. X-rays have a wavelength from 0.01nm to 10nm. The numerical aperture (see later) of the optics is 0.33. High-NA EUV A machine under development by ASML is the high-NA EUV machine which is expected to cost US$300 million. The numerical aperture (NA) is increased from 0.33 in the machines mentioned above to 0.55. These machines will be capable of producing both logic and memory chips in the 2nm technology node – see Fig.32. This machine is expected to be available from late 2023 for R&D customers and 2025 for volume manufacturers. Last month, we discussed multiple patterning and other lithographic techniques to achieve a smaller feature size. Foundries have to decide whether to continue with complicated multiple patterning with non-EUV lithography, or move to EUV lithography with simpler single-patterning. Reticle Optical Column Vacuum Chamber Wafer Handler Light Source Fig.31: part of an extreme UV (EUV) lithography machine from ASML with the covers removed, showing the optical path in purple. This image does not give credit to the size and complexity of the machine; it is roughly the size of a locomotive. Source: ASML siliconchip.com.au Australia's electronics magazine July 2022  19 Fig.32: ASML’s High-NA machine, which should allow even smaller feature sizes to be achieved, enabling the 2nm node. Wafer Stocker To support optimized FF thoroughput Mask Stage 4x increase in acceleration Lens & Illuminator • NA 0.55 for high contract • High transmission Horizontal Source (improved transmission) Compatible with future 0.33 NA sources, power improvements over time Improved Methodology 2~3x improvement in overlay/focus Wafer Stage 2x increase in acceleration Components on ICs Cooling Hood Mitigate wafer heating New Frames Improved thermal and dynamic control with larger optics Now that we’ve fully described how IC dies (also pluralised as dice) are made, let’s look at what they can contain. Apart from transistors and diodes, various other components can be fabricated onto integrated circuits. We will cover some common ones here but cannot possibly cover all existing types. While most of our readers will know how diodes and transistors work, especially if they have read our articles on the History of Transistors in the March, April & May issues (siliconchip.com. au/Series/378), we’ll start with a quick refresher. current to flow in one direction but not the other. As shown in Fig.33, with a reverse-­ biased voltage between the P-doped and N-doped semiconductor material, a depletion region at their junction prevents current from flowing. However, if the voltage is reversed and the device becomes forward biased, as in Fig.34, the depletion zone shrinks until current can flow between the terminals. A P-N junction can be formed in one layer of an IC by doping different areas with P-type and N-type dopants or between differently-doped layers in contact above and below. Diodes Transistors The simplest semiconductor device is the diode. It consists of adjoined areas of P-type and N-type semiconductors. It has the property of allowing A bipolar transistor can be constructed similarly to a diode in an IC but with an extra junction, forming P-N-P or N-P-N connections – see Fig.33: the depletion zone at the junction of P-doped and N-doped semiconductor material in a diode widens when a reverse bias voltage is applied. This blocks current flow. 20 Silicon Chip Fig.35. The emitter is usually doped more heavily than the collector, so those two P or N doped areas are typically created in separate steps. Mosfets are, in a sense, even simpler than bipolar transistors, needing just one type of doped semiconductor (P-type or N-type, depending on whether it’s a P-channel or N-channel Mosfet). The metal or semiconductor gate area is separated from the channel by a very thin insulating layer (usually silicon dioxide) – see Fig.36. The relative simplicity, straightforward biasing requirement and fast switching speeds are why Mosfets are almost exclusively used in digital circuits. JFETs are made similarly to Mosfets, but they do not need the insulating layer since the gate is differently-­ doped silicon, forming a diode junction that is normally reverse-biased Fig.34: with the bias voltage reversed, the diode is forwardbiased. The depletion zone essentially disappears and current can flow freely, with a small voltage drop. Australia's electronics magazine siliconchip.com.au Fig.35: a bipolar transistor can be formed by joining three differently doped areas of semiconductor material, either N-P-N or P-N-P. While the collector (top) and emitter (bottom) use similar material, the emitter is more heavily doped than the collector. Fig.36: Mosfets in ICs are usually 3D structures, but the general principle is the same as this 2D example; the electric field from the gate electrode influences current flow in the channel, between source and drain. Fig.37: an example of a diffused resistor within an IC. In this case, the resistor is diffused P-type material isolated from the substrate by an N-type material layer and covered with an insulating SiO2 layer. It is connected externally via terminals labelled 1 and 2. and hence does not conduct. JFETs are often used in audio ICs as they are low-noise, high-impedance devices. Resistors A resistor is fabricated on an integrated circuit utilising the resistivity of a volume of doped semiconductor or layers of a resistive material – see Fig.37. Resistance values from ohms to kilohms can be produced with a tolerance of about 5% to 20%. Some ICs need higher precision resistors than this (eg, instrumentation amplifiers). They typically use lasertrimmed thin film resistors (more on that below), measuring the resistor’s actual value and adjusting it to achieve the required precision. The resistance can be controlled by several methods such as: 1. A diffusion layer designed to have a particular resistivity. The length, width, diffusion depth and concentration of the layer determine the resistance. Only relatively low resistance values can be produced by this method, but they can be produced at the same time as transistors, so it is economical and common. Higher resistances can be produced by a zig-zag pattern in the diffusion region. Poly-silicon can also be used to create resistors. 2. An epitaxial resistor, used for higher resistance values, is made by depositing a layer on top of the substrate between two metal contacts. 3. A pinched resistor, where the cross-section of a diffused resistor is reduced to increase the resistance. 4. A thin film resistor is fabricated by depositing a resistive substance like Nichrome on the semiconductor substrate, making contact with it. Advantages include good high-frequency Fig.38: metal-insulator-metal (MIM) capacitor is built from layers of conductive metals and an insulating dielectric. siliconchip.com.au performance; the value can be adjusted by laser trimming; and a low tempco (temperature coefficient), meaning good stability. A disadvantage is additional processing steps. Capacitor There are several ways to make a capacitor in an integrated circuit. Some standard methods are as follows. 1. The most common capacitor is the MIM or metal-insulator-metal capacitor. It consists of two metal layers with a dielectric layer between them – see Fig.38. They require more process steps than some others to produce. 2. A similar capacitor to the MIM type is the MOM or metal-oxide-metal capacitor (Fig.39). It uses interdigitated electrodes, like two interlocking sets of fingers. The capacitance Fig.39: a metal-oxide-metal (MOM) capacitor can be fabricated in one plane (left) or multiple planes for higher capacitance in a similar area (right). Australia's electronics magazine July 2022  21 Fig.40: a trench capacitor in silicon. This example is a cross-section of a DRAM memory cell using 3D stack technology. The state of each bit in a DRAM memory chip is retained using a capacitor like this. The capacitor here is a polysilicon plate trench type. Original source: Wikimedia user Cepheiden (CC BY-SA 2.0 DE) is created by a dielectric between the fingers, but it can also have multiple layers, so there is capacitance in the vertical direction. The dielectric material is the oxide used in the processing of the IC, so they are typically cheaper and easier to make than MIM devices. 3. A trench capacitor is another way to implement a capacitor in an IC for use in memory devices, as shown in Fig.40. 4. Capacitors in ICs can utilise the properties of a P-N junction, as in diodes, transistors and other semiconductor devices. These are called junction capacitors because such junctions have capacitance. A junction capacitor is a reverse-­ biased P-N junction that can be formed simultaneously with transistors in the fabrication process. It comprises either the collector-base or emitter-base part of a transistor – see Fig.41. The capacitance is proportional to the junction area and inversely proportional to the thickness of the depletion region. The depletion region occurs at the site of the actual P-N junction. The capacitance is also voltage-­dependent, so these capacitors can be used like varicaps. Inductors Inductors are a challenging component to include in an integrated circuit. Firstly, chips don’t usually contain suitable core material. However, there are cases where magnetic materials such as ferrite can be deposited during the fabrication process (see Fig.42). Also, the limited space available makes for a small coil or spiral size and consequently, low values for both inductance and the quality factor or Q. Additional problems include the large chip area taken; the self-resonant frequency is affected by stray capacitance, but it can still be in the GHz range. On-chip inductors are not compatible with all fabrication processes. Coils or spirals on chips are typically 2D (see Figs.43-45), but bond Fig.43: a die micrograph of a planar spiral inductor on a silicon chip. Source: Michael S. McCorquodale et al. (www.researchgate.net/ publication/224169588_A_Silicon_ Die_as_a_Frequency_Source) wires can be used to make a pseudo-3D coil, as shown in Fig.47. Other devices (MEMS) Devices such as force sensors, gyroscopes and other sensors can be built into ICs using MEMS technology (micro electromechanical systems). For more details, see the Silicon Chip article on MEMS devices (November 2020; siliconchip.au/Article/14635). Connecting the chip to the outside world Traditionally, the chip is connected to a pre-fabricated ‘lead frame’. Connections are made from exposed metal areas on the die to those leads, usually via ‘bond wires’. Both the chip and lead frame are then encapsulated in plastic (or sometimes in a metal can, or even not at all). The bond wires that connect the silicon die (chip) to the package leads have traditionally been made of gold. Other possible materials are aluminium, copper and silver. 200μm 200μm Ferrite film (c) Coils Fig.41: this shows how a P-N junction can be used as a junction capacitor. The capacitor terminals are labelled 1 & 2. 22 Silicon Chip (a) (b) 4μm Fig.42: an on-chip inductor, without and with ferrite film, to act as the magnetic core. Source: https://doi.org/10.1155/2013/832401 (CC BY 3.0) Australia's electronics magazine siliconchip.com.au Fig.44: an annotated image of a chip that operates on the 2.4GHz ISM frequency band, showing on-chip inductors. Image source: H. Jhon et al. (https://ieeexplore.ieee.org/ document/4336140) Fig.45: a chip designed to operate at 390GHz, including tiny inductors. There are at least 14 inductor/transformer pairs in the section labelled “PA+Multiplier”. This die is about 2mm x 1mm. Source: A. Standaert et al. (https:// ieeexplore.ieee.org/document/9056947) Gold is now more expensive than ever, so copper is used for many bond-wire applications today. Still, it requires extra precautions such as an oxygen-free atmosphere to ensure the copper does not oxidise. Extra-highpurity copper is used as the hardness of regular copper is too high. As a lowcost alternative to gold, aluminium can also be used for wire bonding. Ball bonding is a variation of wire bonding. It is a process used to bond gold and copper wires with a combination of heat, ultrasonic energy and pressure. For aluminium wedge bonding, ultrasonic energy and pressure fuse the aluminium wires to aluminium pads (see Fig.46). Controlled collapse chip connection (C4) or ‘flip chip’ (see Figs.48 & 49) is another way a silicon die can be connected to other devices or a carrier package. Solder bumps are deposited onto the die, then the die is turned upside-down (hence “flip chip”) and aligned to corresponding ‘lands’ (pads). Heat is then applied to flow the joints. There are now also technologies that reduce the size of, or eliminate the need for solder bumps altogether. These are important for multi-chip module/chiplet technology, to be discussed next month. The carrier package to which the die is bonded typically is attached to a PCB via a ball grid array (BGA) – see Figs.49 & 50. With a BGA package, the entire area of the carrier package can be covered with connectors, not just along the edges as in more traditional siliconchip.com.au Fig.46: this image shows a chip where aluminium wedge bonding has been used to attach the leads to the chip. Source: Australian National Fabrication Facility, Queensland Node (https://anff-q.org.au/wire-die-bonding-technicalseminar/alu-wedge-bonding-on-chip/) Fig.47: a model of an inductor made on an IC with bond wires. Source: JongWan Kim et al. (www.mdpi.com/1424-8220/7/8/1387/htm – Open Access) Australia's electronics magazine July 2022  23 Fig.48: controlled collapse chip connection (C4). Original Source: Wikimedia user Twisp (public domain) Fig.49: an Intel Celeron CPU with the silicon die attached to the carrier via C4 bonding. The carrier is BGA soldered to the circuit board. Source: Wikimedia user Alecv (CC BY-SA 3.0) packages like dual in-line or quad flat-pack. Once the IC has been connected to the lead frame, a ceramic or plastic layer is often added to protect the die, leaving only the ends of the leads exposed. Plastic packages are now almost ubiquitous because they cost less than ceramic but still offer excellent protection. The plastic used is typically epoxy-cresol-novolak (ECN), as it is strong with very good heat and moisture resistance. The main advantage of ceramic packages is better heat dissipation; they act less like a heat insulator than plastic. In some very low-cost devices like calculators, rather than packaging the silicon die, it is glued to the PCB and bond wires are added to connect it directly to PCB tracks. For protection, a blob of molten plastic (possibly ECN) is deposited on top. This can be cheaper than packaging each individual IC for devices produced in very large numbers. Early IC packaging The first ICs, such as Fairchild’s Micrologic range, were housed in modified cylindrical transistor cans with extra leads added. This was not an efficient way to utilise space on PCBs. Then, in 1962, Yung Tao at Texas Instruments invented a 10-lead 6.4×3.2mm (1/4in x 1/8in) “flat pack” (Fig.51) to better utilise available space for aerospace equipment. These packages were derivatives of existing designs. Integrated circuits are still available in similar packages. That was followed by the development in 1965 of the ceramic dual in-line package by Don Forbes, Rex Rice and Bryant (“Buck”) Rogers at Fairchild Semiconductor. This is the familiar package with rows of pins on each side of a rectangular body, the pins being 0.1in (2.54mm) centre-­ to-centre and bending by 90° to meet the PCB. These dual-inline packages (DIP) revolutionised computer and circuit board manufacturing because they simplified the layout and enabled automatic insertion. This package type is still in common use, but its use has diminished this century due to the increasing use of surface-mounting packages, which do not require holes to be drilled in the PCB and can be soldered on both sides. Australian microchip fabrication There has been a surprising amount of semiconductor device manufacturing in Australia. A Philips factory opened in Hendon, South Australia, in 1947 (siliconchip. au/link/abdz), and IC manufacture started there in 1970. That business became known as Integrated Electronic Solutions Pty Ltd in 1997, then changed its name to Hendon Semiconductors Pty Ltd in 2007 (visit www. hendonsemiconductors.com.au). They no longer fabricate ICs but currently manufacture thick-film hybrid devices and provide other design and manufacturing services. In 1965 (some sources state 1964), Fairchild Semiconductor established a facility in Croydon, Victoria, to manufacture transistors and diodes and later, make ICs in ceramic dual in-line packages (an advert from Fairchild has been reproduced in Fig.52). Like most Australian electronic manufacturing, it closed in 1973 in part due to a cut in tariffs on imported electronic components. However, parts of it were spun off into Hybrid Electronics Australia which was still operating until a few years ago. Security of mask designs The security of IC mask design files has to be considered. They are possibly vulnerable to viruses if appropriate precautions are not taken and malicious parties are able to modify them. Quoting from the article at siliconchip.au/link/abeb: The possibility that an undetected piece of binary code can be inserted within an OASIS file with no restrictions on its size or its content, indicates an undeniable vulnerability to viruses, trojans and worms...there are already some cases where viruses have been propagated through pure data files because of lax security on the part of users. This could enable a hostile state actor to insert features into ICs to enable acts of espionage. There have been rumours that this may have already happened, but there is no confirmation as far as we know. For more information, see the research presentation PDF “Stealthy Dopant-Level Hardware Trojans” at siliconchip.au/link/abec 24 Silicon Chip Australia's electronics magazine Fig.50: a BGA footprint on a PCB after removal of an IC. Source: Wikimedia user Janke (CC BY-SA 3.0) siliconchip.com.au Fig.51: flat pack integrated circuits used in the Apollo guidance computer. This demonstrates that SMD packages have been around for a while! Source: NASA (public domain) Fig.52: a Fairchild Semiconductor advertisement for dual in-line package ICs from Electronics magazine, 13th of December 1965. AWA produced several devices at their factory in Rydalmere, NSW, but that facility was taken over by Philips in 1970 and closed. Silanna Group (https://silanna. com/) was founded in 2006 and is said to be Australia’s only semiconductor design and manufacturing company. To quote Silanna: With its head office in Brisbane and additional operational, manufacturing and design centres in Sydney, USA, UK and Singapore, Silanna supplies high-technology microelectronic chips to the global communications, space, defence and medical markets. The company’s silicon-on-sapphire radio-frequency antenna switch, for example, is used extensively in smart phones and space satellites, and in NASA’s Mars rovers. Unfortunately, Silanna did not respond to our request for more information about their activities in Australia. The Australian National Fabrication Facility (www.anff.org.au) was founded in 2007 “to provide access to micro and nanofabrication equipment, essential to Australia’s scientific future” … “and now represents an investment of more than $400m in research infrastructure made by Commonwealth and State Governments, as well as partner organisations”. The ANFF has 500 pieces of fabrication equipment for micro- and nano-scale devices over 20 sites. They employ 100 experts and help about 3000 users with various fabrication projects each year. For further information about transistor and integrated circuit manufacturing in Australia, refer to the article by Bernie O’Shannassy at siliconchip. au/link/abe0 – the rest of that website is also excellent. You can view an ABC Australia Four Corners program from the 25th of January, 1968, about the “computer age” and concerns about losing jobs to computers (online at https://youtu.be/ qKKMTm-ixZE). The Australian Computer Museum Society (ACMS) Sydney has a website at https://acms.org.au/ There is also the Museum of Computing History in Melbourne; website at siliconchip.au/link/abe1 Australia’s first homegrown stored memory computer, the fourth in the world, and the oldest surviving computer is CSIRAC in Melbourne, see siliconchip.au/link/abe2 The HP Computer Museum in Melbourne is unfortunately not open to the public, but you can see their website at www.hpmuseum.net/index.php Coming up The third and final article in this series next month will concentrate on the current state-of-the-art in integrated circuits, which is multi-chip modules. That is where multiple silicon dies are joined together in a single package to effectively form one very large ‘chip’. This allows for much more powerful devices, increases yields (reducing prices) and adds a lot of flexibility to manufacturing. Interesting links It is actually possible to “see” current flow in an integrated circuit die by observing its operation with an electron microscope. This technique is called voltage contrast. This is demonstrated in the first three points below: ● “Voltage Contrast in the Scanning Electron Microscope - Cambridge Instruments/BT” https://youtu.be/ NYyOphvd8eQ ● “Viewing an active electronic circuit with a scanning electron microscope” https://youtu.be/eoRVEw5gL8c ● Using the voltage contrast technique to see active electrical lines in a chip (PDF): siliconchip.au/link/abed ● “Zoom Into a Microchip (Narrated)” https://youtu.be/Knd-U-avG0c ● “Zoom in on the chip in your smartphone” https://youtu.be/2z9qme_ygRI ● “Catching a single Transistor - We’re looking inside the i9-9900K” https://youtu.be/WOZqoTuAGKY ● An excellent tour of one of Intel’s most advanced fabs (but highly censored): https://youtu.be/2ehSCWoaOqQ ● Here’s a fascinating YouTube channel about home-made ICs: www.youtube.com/c/SamZeloof ● The Computer History Museum in California (https://computerhistory.org/) contains much of the collection of the now-closed Computer Museum that was in Boston. There’s also the Intel Museum in Santa Clara, California; see siliconchip.au/link/abee siliconchip.com.au Australia's electronics magazine July 2022  25 Can you work out the circuit of a fabricated chip by looking at it? Supposing you were prepared to put a tremendous amount of work into ‘reverse engineer’ a chip, could you do it? According to Ken Shirriff, who does it as a hobby, you can, at least for older chips (his blog can be found at www. righto.com). He has developed his own methodology – see the video titled “Reading Silicon: How to Reverse Engineer Integrated Circuits” at https://youtu.be/aHx-XUA6f9g Using his techniques, Ken even managed to solve the mystery of how, in 1974, Sir Clive Sinclair took a simple fourfunction calculator chip from Texas Instruments, shown in Figs.53 & 54, and reprogrammed it to perform scientific calculations. The competing calculator, the HP-35, used five complex chips to do the same operations. Texas Instruments staff were amazed. It was the first affordable scientific calculator. See the story at siliconchip. au/link/abe3 The techniques shown would not likely work in modern high-density CPUs and GPUs because the feature size is much smaller than the wavelength of visible light, so you would not be able to resolve the features with a light-based microscope. An electron microscope would be another story, but how many people have one of those lying around? Also, modern chips have many more layers. The lower layers would not be visible, not to mention the staggering amount of work trying to work out what the billions of transistors and other components did. You can download many die photos for analysis from the following websites: ● https://zeptobars.com/en/ ● http://visual6502.org/ ● http://www.siliconpr0n.org/ You can see an extraordinary simulation of what happens inside a MOS Technology 6502 processor as it is executing code at http://visual6502.org/JSSim/index.html Also see the video titled “Reverse Engineering a simple CMOS chip” at https://youtu.be/FMdYuGpPicw Ken Shirriff has also reverse-engineered the 555 timer chip, said to be the world’s most popular IC, with billions of copies sold. He has identified the chip’s functional elements, as shown in Figs.55 & 56. He has also created an interactive explorer where you can click on parts of the chip, and the corresponding part of the circuit is highlighted. See siliconchip.au/link/abe4 Another example is when AMD reverse engineered Intel’s 80386 CPU to create the Am386 line, which was marketed SC as being 100% compatible with Intel’s processor. Comparator Current mirrors Discharge transistor Voltage divider Output driver Flip flop Comparator Fig.53: a labelled image of the TMS0805 chip used in the 1974 Sinclair Scientific Calculator. The mask was used to reverse-engineer the chip and its instruction code. Source: Ken Shirriff Metal lines Fig.54: a small portion of the instruction ROM of the TMS0805 chip used in the 1974 Sinclair Scientific Calculator, showing how the presence or absence of transistors stores individual bits. Ken Shirriff used this imagery to determine the brilliant code the calculator ran. Source: Ken Shirriff 26 Silicon Chip Transistors Silicon lines Figs.55 & 56: the functional blocks of an LMC555 chip, as determined by Ken Shirriff, and the corresponding internal circuit diagram (above). Australia's electronics magazine siliconchip.com.au