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IC Fabrication Image Source: https://pr.tsmc.com/english/gallery-fabs-inside – Taiwan Semiconductor Manufacturing Co., Ltd. from inception to cutting-edge technology We take an in-depth look at the technology this magazine is named after: silicon chips, also known as integrated circuits or ICs. They are critical to most modern technology, and it has taken decades to get these devices to the pinnacle of performance they have achieved. But the technology has not stopped advancing yet! Part 1 – History & Manufacturing – By Dr David Maddison T his three-part series describes IC (integrated circuit) technology. Given their incredible complexity, we can only really scratch the surface of the fascinating and highly advanced manufacturing methods required. Arguably, this technology is the most advanced ever developed. This first article covers the early history of ICs, IC design, silicon wafer production, fabrication and lithography. Next month, the second part will 12 Silicon Chip focus on how IC technology has improved over time, including production nodes, transistor counts, and wafer sizes. It will then describe the extreme UV (EUV) lithography technology that is the current top-tier technology behind advanced ICs like computer CPUs. That article will also look at what components can be fabricated within an IC and how they are made, how ICs are packaged, Australian Australia's electronics magazine manufacturing and some other interesting aspects of the field. The third and final part will cover the latest IC technology such as FinFETs, GAAFETs, stacked dies and multi-chip modules. It will also discuss the challenges of improving this technology into the future. The transistor’s development The development of the planar transistor was a prerequisite for successful siliconchip.com.au integrated circuit construction. We covered the history of transistors in detail, including planar transistor manufacturing, in the March, April and May 2022 issues (siliconchip.au/ Series/378). The field of integrated circuits is vast and developing rapidly. We cannot possibly mention every possible technology, as a comprehensive survey would require thousands of pages of text! But we will attempt to cover all the critical aspects of IC design and fabrication. Making a single IC is a long, multistep process. Advanced chips like computer CPUs (central processing units) and GPUs (graphics processing units) are reported to take up to 15 weeks. Over the last few years, the industry average for advanced 7nm, 10nm and 14nm devices has been 11-13 weeks. Those times are for the actual manufacturing process, from the growth of the silicon crystal that forms the wafer to the finished product being ready for sale. But they do not include the tens of thousands (or much more) hours of research and development for the chip design itself. There is an adage that the first chip costs millions of dollars to produce (due to the cost of research and fabrication equipment), but subsequent copies cost only cents or perhaps dollars per piece (depending upon complexity). The modern production of ICs is almost entirely automated, using ultrapure materials in extremely clean facilities with extensive atmospheric and other controls to eliminate dust contamination. One advantage of automation is that it means fewer workers shedding skin cells, hair or other detritus that would affect production! Early IC history Combining several electronic components into a single physical device was tried with valves in the 1920s to evade a “tube tax” in Germany. Reducing the number of valves meant less tax on the radio. For example, the Loewe 3NF contained three triode valves, two capacitors and four resistors in one glass envelope (July 2020; siliconchip.au/Article/14513). In 1949, just one year after the transistor was patented, German Werner Jacobi filed a patent (published 1952) for an IC style transistor amplifier. On May 7th, 1952, British engineer Geoffrey Dummer proposed a device with several discrete components on a single semiconductor wafer. He wrote: “With the advent of the transistor and the work on semi-conductors generally, it now seems possible to envisage electronic equipment in a solid block with no connecting wires. The block may consist of layers of insulating, conducting, rectifying and amplifying materials, the electronic functions being connected directly by cutting out areas of the various layers.” This is regarded as the first description of the modern IC. However, he did not claim to be the inventor of the IC. Sidney Darlington of Bell Labs was awarded a patent in 1953 for a monolithic device with more than one device on a single semiconductor crystal (siliconchip. au/link/abdn). That patent would be one of the first for an IC had the patent lawyer not insisted on limiting it to two devices. In 1957, Yasuo Tarui of Japan produced a similar device, a “quadrapole” transistor, but unlike modern ICs, the transistors were not electrically isolated. In 1957, Harwick Johnson was awarded a patent for a “Semiconductor phase shift oscillator and device” (siliconchip.au/ link/abdo), on one ‘chip’ of semiconductor material, in accordance with the modern concept of an IC. This invention does not get the acknowledgement it deserves. Three significant factors associated with the commercialisation of ICs toward the end of 1958 were: a) The development of a hybrid IC by Jack Kilby of Texas Instruments; patent awarded in 1964 (siliconchip.au/link/abdp). Unlike Johnson’s device and modern ICs, this one relied on manually placed wires between the devices. Nevertheless, Kilby’s device is usually regarded as the first IC, and he was awarded the Nobel Prize for Physics in 2000 for his efforts. b) Kurt Lehovec of Sprague Electric Company developed a way to electrically isolate individual electronic components on an IC using “P-N junction isolation”. The device is surrounded by a material with the opposite doping to the substrate. A reverse-bias voltage is applied to the junction, creating a region with few charge carriers. A patent for this was awarded to Lehovec in 1962 (see siliconchip.au/link/abdq). c) Fairchild co-founder Robert Noyce developed the concept of the monolithic IC with diodes, transistors, capacitors and resistors in silicon, with aluminium interconnects and a protective silicon dioxide coating (see the diagram at lower left reproduced from siliconchip.au/link/abdr). Noyce died in 1990; otherwise, he might have shared the Nobel Prize with Kilby. In addition to the above patent, Jean Hoerni developed the planar process for fabricating transistors and other semiconductor devices (the patent was awarded in 1962; siliconchip.au/link/abds). This process was critical for Noyce’s work and he improved the process. The “traitorous eight” Jean Hoerni initially worked for William Shockley, but Shockley’s behaviour led Hoerni, along with seven others, to leave Shockley in 1957 to found Fairchild Semiconductor. They became known as the “traitorous eight” (see https://w.wiki/522K). Why use integrated circuits? Compared to devices built with discrete components, ICs allow for much smaller, simpler, more reliable and less expensive devices. This is because most or all of the parts can be made in a single process. Also, modern devices with extremely high numbers of components (in the billions), such as computers and mobile phones, would be practically impossible to make without ICs. They would be incredibly expensive and huge, even if it were possible to build them. siliconchip.com.au Diagrams from Robert Noyce’s (Fairchild Semiconductor) US Patent 2,981,877 (filed 1959, awarded 1961) for “Semiconductor Device-and-Lead Structure”. This is regarded as the first practical IC. Australia's electronics magazine The “traitorous eight”, from left to right: Gordon Moore, C. Sheldon Roberts, Eugene Kleiner, Robert Noyce, Victor Grinich, Julius Blank, Jean Hoerni and Jay Last. Source: Wayne Miller, Magnum Photos (https://w.wiki/53GC) June 2022  13 The first operational IC Fig.1: a die photo of the Micrologic uL903 from 1960, one of Fairchild’s first commercially produced ICs. It is a 3-input NOR gate used in the Apollo guidance computer. It contains four resistors and three transistors. The first operational IC was produced on the 27th of September, 1960, by a group at Fairchild. They were led by Jay Last and used ideas from Noyce (monolithic IC) and Hoerni (Fig.1). This led to a patent dispute with Texas Instruments, which held Kilby’s hybrid IC patent. This was eventually resolved by industry cross-licensing in 1966. Historians do not share a strong consensus on whether a specific individual invented the IC or whether the honour should go to multiple inventors. This author thinks multiple contributions should be acknowledged. The first commercial IC was released to the general public in March 1961, a type F flip-flop under the Micrologic brand, followed by more types in 1962 – see Fig.2. Texas Instruments released their first commercial devices in October 1961, the Series 51 DCTL “fully-­ integrated circuit” family (siliconchip. au/link/abdt). Components in ICs As you would expect, transistors can be fabricated in ICs, including bipolar transistors, Mosfets and JFETs. Most modern processes can produce either polarity of each device (ie, NPN, PNP, N-channel or P-channel). Naturally, diodes can also be made, as they are usually just a single P-N junction. That can include zener diodes, depending on the fabrication process being used. But to make a truly useful IC, it is also necessary to include other components like resistors, capacitors and inductors, and that is certainly Fig.2: IC die patterns from Fairchild Semiconductor, released in October 1962 following the uL903, including (B) a buffer, (C) counter adaptor, (F) flip-flop, (G) gate, (H) half-adder, S) half shift register. Some time after that, they added the 4-input gate (G1) and dual 2-input gate (D). Source: Fairchild Semiconductors siliconchip.au/link/abej 14 Silicon Chip possible, as we will describe next month. But first, we’ll explain how an IC is made, as the limitations of that process determine how these components must be fabricated. Silicon doping Like transistors and diodes, integrated circuits are mainly made of P (positive) and N (negative) doped silicon, conductive metals like aluminium and copper, and insulators like silicon dioxide. We covered doping in the aforementioned series on transistors, so we will only briefly cover it here. Doping alters the electrical conductivity and other properties of the semiconductor material. The semiconductor is typically silicon but may also be: • silicon-germanium • gallium arsenide, in microwave integrated circuits, infrared LEDs, laser diodes and solar cells • gallium nitride, in blue LEDs and other opto-electronic, high-­ frequency and high-power devices • cadmium telluride in photovoltaics and infrared optical windows • gallium phosphide, as used in LEDs Doping involves introducing different metals into the silicon crystal structure, from around one atom in 100 million for “light” doping to one in 10,000 for “heavy” doping. Either way, only trace amounts of the dopants are used. Metals (conductors) conduct electricity because of the free electrons provided by each atom in a metal crystal structure. Semiconductors lack free electrons, but doping the semiconductor with metal atoms introduces extra charge carriers. Therefore, doping One of the pickup tools used to move groups of wafers around the factory. Picture: Bosch Australia's electronics magazine siliconchip.com.au Fig.3: an overview of the VLSI design process. VHDL and Verilog are hardware description languages (HDL). Original source: www.eng.auburn. edu/~strouce/class/elec4200/CADtools.pdf RTL is Register Transfer Level and AUSIM and PSPICE are both circuit simulators. increases the electrical conductivity of the semiconductor. It is possible to make a heavily-­ doped semiconductor conduct almost as well as some metals. This means that it is possible to replace metal tracks with heavily-doped semiconductor material in integrated circuits. Unlike metals, where the charge carrier is almost always an electron, in semiconductors, the charge carrier can be an electron or the absence of an electron, called a “hole”. N-type (negative) doping means the majority charge carrier is a negatively charged electron. P-type doping is where the majority charge carrier is a hole with a positive charge. Typical P-type dopants used for silicon are boron, aluminium, gallium and indium, while N-type dopants are antimony, arsenic, bismuth, lithium and phosphorus. They have advantages in different applications. Other semiconductors use dopants such as carbon, chromium, germanium, lithium, magnesium, nitrogen, phosphorus, selenium, sodium, sulfur, tellurium, tin and zinc. The conductivity of semiconductors in integrated circuits can also be controlled by nearby electric fields (as in Mosfets) or by charge carrier injection (as in bipolar transistors). This means that the current flow through a junction can be electronically controlled, either continuously in an analog circuit, or in an on/off fashion in a digital circuit. The designer specifies what is required using a language like Verilog or VHDL, and the computer then figures out what combination of tiles provides an equivalent function. It lays the tiles out on a grid, calculates the routing between the tiles and generates the physical structure. The result is a set of masks that can be run through simulations to verify that the chip will behave as expected. IC design These masks or photomasks are then Before a chip can be made, it must be used to transfer the design to silicon. designed. As the most complex VLSI An IC mask layout view of a simple designs now contain billions of tran- operational amplifier is shown in sistors, the process is heavily reliant Fig.4, while an actual mask is shown on computers and software tools. The in Fig.5. exact design procedures are many and The highest performance chips varied and beyond the scope of this require significant ‘bottleneck’ areas article, but an overview is provided (such as multiplier-accumulators) to in Fig.3. be designed by hand as they can be Briefly, the design process is usu- made smaller, faster and more effially a combination of computer-aided cient. These hand-made pieces can and manual design. Simpler, less-­ be integrated into the synthesised demanding digital chips can be made designs. It is also possible to manualmost entirely using a ‘tile-based’ ally modify a synthesised design or scheme. Each tile might be a different give the software ‘hints’ to produce a type of logic gate, memory cell, multi- more optimal result. plexer, adder, multiplier etc. The industry-standard digital file Fig.4: a mask layout of a simple IC, an operational amplifier. Red is polysilicon; blue is metal layer 1; green is N-doped Si; brown is P-doped Si and the Xs are cross-layer “vias”. The large square on the right is a capacitor. Source: Wikimedia user Atropos235 (CC BY-SA 2.5) siliconchip.com.au Australia's electronics magazine Fig.5: an IC photomask. Source: Wikimedia user Peellden (CC BY-SA 3.0) June 2022  15 ► Fig.7: the process starts with purified silicon rods (left). Silicon from trichlorosilane gas is deposited onto them (centre), then they are broken up and formed into large silicon crystals by the Czochralski process (right). Source: Silicon Products Group GmbH ► Fig.6: a 3D view of a small “cell” (a standard design element of an IC) generated with the ShapeshifteR software from GDSII mask files. There are three metal layers plus vertical interconnects, with silicon gates in a reddish colour on top of the multi-coloured bulk silicon. The insulating material has been removed from this image. Source: David Carron (public domain) format for masks which can be transferred from designer to foundry is called “Graphic Design System” (GDS, introduced 1971) and “GDSII” (introduced in 1978). Since 2004, OASIS (Open Artwork System Interchange Standard) has been used, which can handle much larger mask sizes than GDSII. The GDSII files for the mask description of a ‘system-on-a-chip’ device like a mobile phone processor (as an example) can exceed 200GB. Fig.6 shows a 3D view of a ‘cell’ within a silicon wafer produced by software called ShapeshifteR that takes a mask design from a GDSII file and renders it into a 3D representation and cross-section of the actual chip. See http://shapeshifter.free.fr/ index.htm A ‘fabless’ design house does not manufacture chips but sends its mask files to a ‘pure play’ (fabrication only) foundry to have its design implemented in silicon. However, companies like Intel also specialise in both design and fabrication. Silicon wafer manufacturing Apart from design, the first stage of IC manufacture for silicon devices is to grow a near-perfect silicon crystal. Quartz ore called quartzite (basically silicon dioxide, SiO2) is the major component of most beach sands. It is extracted from quartz mines and refined to make silicon. Quartzite is crushed and then mixed with coke (coal that had previously been heated without oxygen). The mixture of quartzite and coke is added to an electric arc furnace where high temperatures of around 2000°C are produced. The carbon in the coke reacts with the oxygen in the quartzite, removing it. The result is an impure form of silicon that needs further refining. The silicon is then mixed with gaseous hydrochloric acid to form trichlorosilane, HCl3Si. This is a gas at the temperatures used so that it can be further purified by fractional distillation. The purified trichlorosilane gas is then mixed with hydrogen in a chamber with purified silicon rods electrically heated to 1150°C. It decomposes and is deposited as pure silicon on the rod surfaces to make polysilicon (many crystals as opposed to a single crystal) with a purity of 99.99999% (“seven nines”) or even ten or eleven nines. The polysilicon is then broken up to make a feedstock for the crystal growing process. Dopant metals such as antimony, arsenic, boron or phosphorus are added to the polysilicon to give the silicon the required electrical properties. This is called the Siemens process (Fig.7). It is the most commonly used process, but it uses a lot of energy; other processes have been developed, Fig.8: the Czochralski process for growing single large pure silicon crystals. 16 Silicon Chip Australia's electronics magazine siliconchip.com.au Picture: Bosch Picture: Taiwan Semiconductor Manufacturing Co., Ltd. such as a fluidised bed reactor. Once purified polysilicon is broken up, it is melted in an inert atmosphere and a ‘seed’ crystal attached to a puller rod is introduced into the melt and slowly withdrawn. The melted silicon solidifies and crystallises onto the seed crystal (set up with a preferred crystal orientation). The growing crystal is withdrawn from the melt as the rod is raised (see Figs.8 & 9). This is called the Czochralski process. It is economically beneficial, up to a certain point, to make crystals with as large a diameter as possible to maximise the number of devices that can be made at once on a single slice of crystal, known as a wafer – see Fig.10. Silicon wafer preparation Once the crystal has been grown, it is sliced into thin wafers, and the surface and edges are ground, polished and cleaned to make uniformly-sized wafers. A typical wafer cut from a 300mm diameter crystal is 0.775mm thick, weighs 125g and 640 10mm x 10mm dies (chips) can be made on it. The planar process The key concept of IC fabrication is the “planar process”. This was initially developed by Fairchild Semiconductor in 1959, and it involves considering the construction of an IC as one (or, nowadays, a series of) 2D plane(s). Individual areas within each plane are either joined together or insulated from each other. Various types of junctions can be created this way, such as P-N, N-P-N or P-N-P. This planar approach means that lithography can be used, where images are projected onto the wafer to form the circuit with the aid of light-­sensitive chemicals and photoresist coatings. This involves selective etching, deposition, implantation and other alterations of desired areas of the wafer. Wafers come in multiple different sizes from 25mm up to 450mmdiameter. The thickness of the wafer is important as it needs to be strong enough not to break during handling; a typical thickness for 300mm wafers is 775μm. Wafers can be stored in “desiccants” or transfer machines as shown above. Conductors on ICs can be made by the deposition of metals or the selective doping of semiconductor areas (eg, silicon). Insulators can be made by oxidising silicon to produce silicon dioxide or using the technique of P-N junction isolation. A silicon dioxide insulator can also be etched to expose underlying material for alteration in various ways. Semiconductor junctions can be made by doping specific regions and depositing additional material on top of those regions. Wafer processing steps Processing a wafer to produce ICs involves four categories of operations as follows. These may be done multiple times, up to around 300 steps for the most complex devices, and in various orders. #1 Deposition This involves depositing coatings ► Fig.9: a silicon crystal grown by the Czochralski process at Raytheon in 1956. The melt is heated by the coils of the induction heater; here, the temperature is being measured. In this case, a 25mm diameter crystal was grown, but today 300mm diameter is typical, and 450mm is under development. Source: Radio and Television News, May 1956 (public domain) Fig.10: a silicon ingot on display at the ► Intel Museum, 300mm in diameter. That is one of the current industry standards, starting around 2002, and it is a compromise between size and productivity. Source: Wikimedia user Oleg Alexandrov (CC BY-SA 3.0) siliconchip.com.au Australia's electronics magazine June 2022  17 Fig.11: one method of exposing individual areas of a silicon wafer with a mask. The lens shrinks the image from the mask to the die size. A more advanced process is ‘step and scan’, where an individual die is exposed through a narrow slit which is scanned to obtain tighter focus and smaller feature size. onto the wafer, such as oxidising the silicon to create an insulating silicon dioxide layer (passivation), deposition of metal conductors, silicon, or other semiconductor materials. The processes to do this are varied and include: • Physical and chemical vapour deposition • Electrochemical deposition • Molecular beam epitaxy • Atomic layer deposition • Thermal oxidation of the entire wafer • LOCOS (local oxidation of silicon), where individual areas of the chip are selectively converted to a silicon dioxide insulating layer that either totally block light or let it all through, unlike a monochrome photograph/slide, where there are grey areas of partial light transmission. Before the 1980s, an “aligner” was used that had large masks containing many duplicate die images so that an entire wafer could be exposed at one time. The pursuit of higher resolution (smaller feature size) meant that around the 1990s, the aligner was replaced with a “stepper”. Only a single die image was produced at a time, with the light focused onto a single area on the die. The mask is moved (stepped) across the wafer to repeat the pattern. In the pursuit of even higher resolution, since the 2000s, the stepper has been replaced with “step and scan” systems where only a small portion of #2 Patterning This involves laying down the desired circuit pattern on the wafer or deposited or etched materials. This is done using a photographic-­like process called lithography (see Figs.1113). The mask, which is like an old photographic slide or negative, is placed between an appropriate light source and the die, and an image is projected onto the die, which has been coated with photoresist. Note that the mask is much larger than the die size; a reducing lens is used to shrink the mask size to the die size. Also, the mask usually has areas 18 Silicon Chip A photo of a clean room at Bosch’s semiconductor factory in Dresden, Germany. Picture: Bosch – www.bosch-presse.de/pressportal/de/en/bosch-semiconductormanufacturing-in-dresden-225609.html Australia's electronics magazine siliconchip.com.au Fig.12: the basic process of photolithography using photoresist. Original Source: Wikimedia user May lam (CC BY-SA 4.0) a mask is exposed at one time, enabling better focusing. Before patterning, the die will have been prepared with a light-sensitive coating called photoresist. In the case of a positive photoresist, the photoresist regions that are exposed to the light become soluble and can be washed away, leaving the unexposed photoresist behind. A negative photoresist will do the opposite. After certain photoresist regions are washed away, the wafer itself can be etched in those areas or processed in some way, such as being doped. After that, the remaining photoresist can be removed. Using shorter wavelengths of light allows for higher pattern resolutions. These days, the density is so high that the light is typically in the UV spectrum, or extreme UV (EUV) in the latest systems. Electron beams can be used as an alternative to light sources. Electron beam lithography provides a high resolution, but it has a low throughput, so it is mainly used for low-volume production of semiconductors and the production of photomasks. There may be multiple masks used and multiple exposures between additional etching, deposition and other procedures. Another possible process is contact lithography, but it is not used for mass production. Figs.14 & 15 will give you an idea of the complexity of the built-up layers of an IC. Figs.16 & 17 are mask and die images of the world’s first microprocessor, the Intel 4004, designed by hand and released in 1971. Consider that modern chips are many orders of magnitude more complicated than that! Other lithographic processes of note, but not currently used for mass production, are: • displacement Talbot lithography (DTL) for periodic patterns • thermal scanning probe lithography (t-SPL), where nanoscale structures are generated with a heated probe moved over the surface of a resist coating which is then etched • UV flood exposure, to expose individual wafers on a small R&D scale Fig.13: a simplified version of the etching process using a positive photoresist. Cr is chromium on the mask, while PR stands for photoresist. Source: Wikimedia user Cmglee (GNU FDL V1.2) Fig.14: a simplified version of the processes to produce a portion of a CMOS IC. Note that the gate, source and drain contacts are not usually in the same plane in real devices. Source: Anonymous Wikimedia user (CC BY-SA 3.0) siliconchip.com.au Australia's electronics magazine June 2022  19 • direct laser lithography, a form of maskless lithography, for small scale R&D use • nanoimprint lithography, in which nanoscale patterns are imprinted into a resist by a mould with the desired pattern and then etched #3 Removal Material is removed from the silicon die by wet or dry etching processes or a combination of chemical and mechanical polishing (called CMP for chemical-­mechanical planarisation). The polishing is also used to ensure that the surface of the wafer is atomically flat before the next layer is added. #4 Modification of electrical properties Fig.15: a cross-section of a multi-layer CMOS chip with five metal layers, denoted Layer 1 to Layer 5. There’s a legend at the top; STI is shallow trench isolation, FEOL is front-end of line and BEOL is back-end of line. Original Source: Wikimedia user Cepheiden (CC BY-SA 3.0) This involves processes such as doping selected areas by methods such as diffusion or ion implantation to create the sources or drains of transistors, with P- or N-type dopants, or the creation or modification of insulating areas, such as through oxidation. Ion implanation is a method of doping in which a beam of dopant ions from a particle accelerator is scanned over the wafer, implanting ions in the areas not covered by the photoresist to a controllable depth. The wafer is then annealed in an oven, reforming the crystal structure and ensuring that the ions are evenly distributed. Alternatively, dopants can be introduced to the surface of the wafer via gas-phase or solid diffusion, followed by ‘drive-in’, where the dopants are diffused deeper into the semiconductor material. The wafer is placed in a furnace with an inert atmosphere and heated, diffusing the dopants throughout the areas on which they have been deposited. Similar furnaces can be used to also convert the top layer of semiconductive silicon to the insulator silicon dioxide by heating the wafer in an oxygen-rich atmosphere. Front-end-of-line and back-end-of-line Fig.18: light is diffracted as an incident wavefront of a beam of light (eg, from a laser) passes by an edge, causing potentially unwanted secondary wavefronts and thus light spreading. In photolithography, the edge would be part of the mask pattern. 20 Silicon Chip Australia's electronics magazine The term “front-end-of-line” (FEOL) refers to the initial part of the fabrication process, where the individual components such as capacitors, diodes, resistors and transistors are formed. But it is before metal interconnect layers are deposited to join them electrically. siliconchip.com.au The FEOL process for CMOS (complementary metal oxide semiconductor) includes the following steps: 1. preparation of the wafer 2. electrical isolation of trenches or other selected areas by oxidation of silicon to silicon dioxide or deposition of other dielectric materials 3. well formation (the well is the first layer fabricated of a CMOS IC and may comprise an N-doped well in a P-type substrate; see Fig.15) 4. gate module formation 5. source and drain module formation The gate, source and drain referred to above are the main parts of a field-­ effect transistor or FET. “Back-end-of-line” (BEOL) refers to the second main stage of IC fabrication, where the interconnection of the devices formed in the FEOL process takes place by adding metal layers. It also includes the addition of insulating layers, vias (vertical conducting elements to connect between layers; see Fig.15) or bonding sites for chipto-package connections. Many metal layers can be added in multiple processing steps. You can think of these a bit like the copper patterns on a PCB. Wavelength of light for lithography Over time, as the number of transistors on a chip has increased, lithography has required shorter and shorter wavelengths of light to produce the smaller IC feature sizes. We’ll have some details on the light sources used when we discuss the shrinking process nodes in part two, next month. Features smaller than the wavelength of light As you can see from the above, IC feature sizes are now much smaller than the wavelength of light passing through the mask and illuminating the wafer. You might expect that diffraction effects (spreading out the light and causing images to be indistinct) would prevent accurate patterns from being made on the wafer, and this is indeed the case. So how is this problem overcome? There is a limit to how short the light wavelength can be (to make smaller feature sizes), so there is obviously the desire to minimise this effect. Note also that EUV equipment is expensive. siliconchip.com.au Figs.16 & 17: images of the Intel 4004 microprocessor from 1971 showing a composite image of the masks (light colour) and the die (dark colour). It was a 12mm2 4-bit microprocessor with 2250 transistors and it started an electronic revolution. Source: Tim McNerney (http://alumni.media.mit. edu/~mcnerney/2009-4004/) Fig.19: an illustration of the Rayleigh Criterion, the theoretical limit of resolution. The two blue peaks merge to form a single large (red) peak when they are close together but become separately resolved as they move apart. Original source: Wikimedia user Mpfiz (public domain) Australia's electronics magazine June 2022  21 Fig.20: (a) a conventional binary mask, (b) an alternating phase-shift mask and (c) an attenuated phase-shift mask. The latter two types can provide finer details for the same wavelength of light. Original source: Wikimedia user Oleg Alexandrov (public domain) Diffraction (see Fig.18) is the production of secondary wavefronts that occurs at the edges of an opening when the primary wavefront of a light beam passes through. This happens with projection lithography, which is the dominant form, but does not happen much with contact lithography, although that is not suitable for mass production. There is a fundamental physical limit to resolution defined by the Rayleigh Criterion. The web page at siliconchip.au/link/abdv states, “The Rayleigh criterion for the diffraction limit to resolution states that two images are just resolvable when the centre of the diffraction pattern of one is directly over the first minimum of the diffraction pattern of the other.” see Fig.19. It is not simply a matter of making a design and specifying it be made smaller; significant new problems have had to be overcome each time the process size has been shrunk. The various techniques that have been used to achieve feature sizes smaller than the wavelength of light are: #1 Phase-shift masks Phase-shift masks make diffraction work for you, not against you. Interference is generated by phase differences brought about by different thicknesses or translucency in parts of the mask, to improve contrast on the photoresist and thus resolution. Fig.21 shows the behaviour of light energy with various mask types. A conventional binary mask either transmits light or doesn’t, depending on the region, as shown in Fig.21(a). In alternating phase-shift masks, some regions are made thicker and others thinner. When the thickness is appropriately chosen, the light going through modified areas of the mask interferes with the light going through unmodified regions, improving contrast and resolution – see Fig.21(b). In attenuated phase-shift masks, light is allowed to pass through particular mask sections but attenuated due to partial transmittance of the mask material. The small amount of light allowed through will not cause a pattern on the wafer, but it will interfere with non-attenuated light from other areas to enhance contrast and resolution – see Fig.21(c) & (d). The half-tone mask has transparent and semi-transparent material regions that cause light interference, enhancing contrast and resolution. These masks are easier to make than alternating phase-shift masks. #2 Photoresists To achieve higher resolution, new photoresists have had to be developed. The following factors have to be considered in developing a photoresist: • contrast between exposed and unexposed portions • sensitivity to the wavelength of the light used (the shorter the wavelength of light, the less absorption of light energy) • viscosity • adherence to the substrate • the ability to resist etching • surface tension #3 High numerical aperture lenses Note the projection (also called objective) lens in Fig.11. The lens Fig.21: different mask types with the resulting patterns that appear on the wafer. Note the middle detail missing on the wafer for the binary mask and the added detail in the phase-shift masks. Source: Wikimedia user Shigeru23 (GNU FDL V1.2) 22 Silicon Chip Australia's electronics magazine siliconchip.com.au should gather the diffracted light from the mask. The higher the numerical aperture (NA) of the lens (similar to the f-number in photographic lenses), the more diffracted light that it will gather and the higher the resolution of the image produced. However, the higher the NA, the smaller the depth of focus, requiring extremely precise mask alignment to avoid parts being out of focus. #4 Immersion lithography Another technique is to use immersion lithography, in which the light passes through water rather than air. The higher index of refraction of water means an effective decrease in wavelength of about 33%, enabling smaller feature sizes. #5 Optical proximity correction OPC (optical proximity correction) is a method to compensate for errors due to diffraction or other reasons – Fig.22 shows one example. Calculating the correct patterns for OPC is extremely computationally intensive and can occupy compute clusters for days. #6 Multiple patterning Double or multiple patterning, also known as self-aligned multiple patterning (SAxP), is a complicated and expensive process. It is used to produce photomasks for the highest possible feature density. In multiple patterning, multiple lithography and etch steps are used to achieve higher Note the overhead system as TSMC’s facility and the row of DD-1223V “12-inch” wafer furnaces. Picture: Taiwan Semiconductor Manufacturing Co., Ltd. resolution than could be achieved with a single step. As an example, a double patterning process results in a 30% smaller feature size, but the number of process steps and therefore cost is increased. Double patterning is used to make NAND flash memory (as used in SSDs and SD cards), random access memory (RAM) and the fins in FinFETs, used in many cutting-edge computer chips. There are many different methods of multiple patterning. Double patterning in its original form was also called pitch splitting. Two adjacent features cannot be made closer together than the minimum pitch allowed by the lithographic system; therefore, one set of features is made first, and the second mask is Next month Next month, we will discuss how feature sizes have changed over time and what advances that progress has allowed, including Moore’s Law. We’ll also go into more detail about the silicon wafer sizes and extreme UV (EUV) lithography, plus describe IC packaging and the various components that can be created using the IC fabrication process described above. There is more to come after that, including the latest 3D stacking and multi-chip module technologies. SC Fig.23: a form of multiple patterning called pitch splitting. Three trenches are first etched, then covered in photoresist (top). Then a second exposure is made, and a second set of trenches is etched (middle). The photoresist is washed away, resulting in pairs of trenches that are closer together than a single exposure would allow (bottom). Original Source: Wikimedia user Wdwd (GNU FDL V1.2) Fig.22: in optical proximity correction, the image is ‘precorrected’, so the projected pattern distorted by projection is the desired one. The thicker areas are the desired pattern; the thinner wavy lines do not print. They are called sub-resolution assist features (SRAFs) and improve depth of focus. Source: Wikimedia user LithoGuy (CC BY-SA 3.0) siliconchip.com.au used to create a second set of features. Therefore, the distance between the features can then be less than the minimum pitch of the lithographic system – see Fig.23. Australia's electronics magazine June 2022  23