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Circuit Surgery Regular clinic by Ian Bell Simulation issues with a digital divide-by-two circuit I n response to the Circuit Surgery article on Micro-Cap 12 (December 2020), Ken Wood decided to try to simulate a circuit he had problems simulating years ago. He writes: ‘I was delighted to be alerted to the availability of Micro-Cap 12, and duly downloaded it. I have not toyed with simulators since my professional life circa 1988, where we had a huge Unix machine at work. ‘I have had a little problem in the back of my mind for years: recreating standard logic register functions using just gates. I had no success simulating those circuits back then, so I figured it was worth another go. I designed a simple divide-by-two (output toggles at half the rate of the input) using eight gates, and input it into MC12 (see Fig.1). ‘Running the simulator results in instability (see Fig.2). There are a couple of cross-coupled gates, and with the other signals in the appropriate state this creates a positive feedback loop with delay – which oscillates in the simulator. Experience says this won’t oscillate, it will latch into one state or the other – so I built the circuit and proved it works. The photo shows the breadboarded circuit (built from two CD4011 quad-NAND ICs), powered from 5V and using the 1kHz 5V square wave calibration signal from the ‘scope as a clock. ‘The ‘scope traces are the input at the top, and the output at the bottom – it worked first time, exactly as designed. Fig.3. The Fig.1 circuit built on a breadboard, operating correctly. ‘Is there any answer to this simulation problem? I think it might be due to the models being perfect and creating a timing race hazard, whereas real devices are never perfect. I tried tweaking some of the gate delays, but I haven’t hit on a working combination. ‘So now I know why my simulations didn’t work in 1988. The simulator was regarded as the be all and end all, and it’s a good job I never needed a circuit like this in a professional project, because it would have been diffi cult getting it past a pre-production review without simulator confirmation it would work!’ ‘Before looking at Ken’s circuit and what might be going wrong in the simulation we will go back to basics and look at how flip-flops are built from logic gates, how they work and the problems that can occur with their operation. Fig.1. Ken’s Micro-Cap 12 schematic for his divide-by-two circuit. A B 0 C 1 1 0 0 1 Fig.4. Two inverters in series. A 1 B Fig.2. Micro-Cap 12 simulation results from the circuit in Fig.1 – the solid blocks of colour on the outputs are oscillations which are too fast to see on this timescale. 46 0 A 0 1 0 1 Fig.5. Two inverters in a loop – a bistable circuit, the basis of flip-flops. Practical Electronics | February | 2021 D Q 1 C Q 1 S ym bol C ontrol S 2 D S (IN S ym bol Q 2 ) Q S Q R S 1 Q IN 1 IN 2 (IN R Q Q 1 ) Q Fig.6. Latch circuit and symbol. Fig.7. Set-reset flip-flop. Memories are made of this Think of two inverters in series (see Fig.4). The 1 in (at A) gives a 1 out (at C) and a 0 in gives a 0 out. Consider what happens when we connect the output back to the input (see Fig.5). There is no conflict since the ‘input’ and output are both at the same logic level (there is not really an input anymore). If point A (now the same as C) is made 1, it will stay there indefinitely. If we set A to 0, it will stay at 0. These two conditions are referred to as ‘stable’ states, and the circuit is described as being ‘bistable’. This ability to indefinitely hold one of two possible states is the basis of the static digital memory, where the term ‘static’ refers to the fact that the state is held permanently (as long as power is applied) and does not ‘fade’ or need refreshing. The memory function provided by the circuit in Fig.5 is not particularly useful as there is no input by which it can be given a value to remember; however, we can modify the circuit to achieve this in a couple of ways. First, we could break the loop using a switch while employing another switch to connect the input. Second, gates can be used to modify the logic of the loop in order to enable the state to be set. The way in which switches may be used to set the state of the loop in Fig.5 is shown in Fig.6. This circuit can be implemented in CMOS, where MOSFETs can be used for the switches. The two switches (S1, S2) are controlled together and are arranged so that when S1 is open S2 is closed and vice versa. When S1 is open and S2 is closed the input is isolated and the loop is closed (like Fig.5). The loop stays in its current state and is unaffected by the input. When S1 is closed and S2 is open the input is connected to the output via the two inverters (like Fig.4, and the output will follow the input. When the switches change to S1 open and S2 closed the loop is formed, storing the data. The gate capacitance of the inverters will hold the value while the changeover occurs until the loop locks the stored state in place. The set-reset flip-flop The circuit in Fig.7 replaces the loop inverters of Fig.5 with two NAND gates. If IN1 = IN2 = 1 the circuit is equivalent to the two-inverter loop. However, if one of the inputs is zero the Q output is forced to either 1 or 0, irrespective of the previously stored value. If IN1 = 0 and IN2 = 1 an output of Q = 0 is produced. This is retained when IN1 returns to 1. If IN1 = 1 and IN2 = 0 an output of Q = 1 is produced. This is retained when IN2 returns to 1. The IN1 input going low forces a 0 to be stored and so this input is called reset (R). The IN2 input going low forces a 1 to be stored and so this is called set (S). This type of circuit is called a ‘set-reset’ flip flop (SR or RS flip-flop) and its circuit is often drawn in the form shown in Fig.8 and can be represented by a block symbol, also shown in Fig.8. The set and reset inputs are ‘active low’, hence the bars drawn over them in the diagram. If you connect two NOR gates in the same configuration you get an SR flip flop with active high inputs. There are two SR flip-flops in Ken’s circuit one formed by X2 and X3, and the other by X5 and X7. Practical Electronics | February | 2021 Fig.8. Set-reset flip-flop circuit and symbol. The outputs of either NAND gate in Fig.8 may be used and are complementary (opposite logic levels to each other) and so are labelled Q and Q. However, if we set both inputs to zero then both outputs will go to 1. If we require that the outputs are complementary then this is an ‘illegal’ condition, perhaps implying that our flip-flop is not being used properly – we are effectively asking it to set and reset at the same time, which does not really make sense. However, if we remove one of the active input conditions the remaining one will be applied correctly. For example, if we apply R=0 and S=0 to the flip-flop in Fig.8 and then change to S=1 while keeping R=0 the flip-flop will reset. If the condition where both outputs are 1 does not cause problems elsewhere in the circuit then using the flip-flop in this way may be alright. Unpredictable A far more serious problem occurs if we return both inputs to 1 simultaneously. The flip-flop effectively remembers the last instruction it received (set or reset). If we apply both together and remove them simultaneously, which should it remember, given that it can only store one state? The circuit is symmetrical and there is nothing to indicate what should happen – the response is not defined. It is not a good idea to have a circuit with undefined behaviour, but the SR flip-flop is useful otherwise, so we can make a rule to say, never do this and try to design to ensure it will never occur. However, a real circuit will do something if we remove the set and reset simultaneously and it is instructive to understand what this might be – in case it does occur in something we design. When we simultaneously change both inputs of a NAND SR flip-flop from 0 to 1 we effectively create a situation like the looped inverters in Fig.5, where both have an output of 1. Both inverters will react to their inputs (also both 1) by changing their outputs toward logic 0. If we consider the gate to behave as a Boolean NOT function with a delay, then both inverters will output 0 after their delay time. If they have identical delays, then both will change to 0 simultaneously. We now have the looped inverters in Fig.5 both outputting 0, they will both change to 1 at the same time and we are back to were we started. The process will continue indefinitely – the looped inverters will oscillate as happens in Ken’s simulation. In a real circuit it is unlikely (near enough impossible) that the two inverters (actually NAND gates in the SR flip-flops of Fig.8) will have exactly the same delay. In this situation, the fastest inverter will switch to zero first, at which point the inverter loop will be in one of the stable states shown in Fig.5. The state is stable, so it will stay there – no oscillation will occur. The problem is that in general we will not know which gate is fastest, so the outcome is unpredictable – the flip-flop may set or reset, but we do not know which. This unpredictability may mean that a physical circuit behaves differently at different times, or different copies of the circuit do different things – both could have very serious consequences. However, it is also possible that (almost) 47 at the loop behaviour. The 10fF (10 femtofarad, 10 ×10–15F) capacitors represent the capacitance of the wiring linking the inverters (as it may be on an integrated circuit). The simulation results in Fig.10 show that the average propagation delay of the two inverters is about 175ps (175 ×10–12s). Fig.11 is the circuit from Fig.9 reconfigured to form a loop of inverters, as in Fig.5. We no longer have the input signal from V2 and we need to specify the voltages on the inverter inputs/outputs at the start of the simulation using the SPICE .ic (initial condition) directive. By setting initial conditions where both inputs/outputs are at logic 1 (5V in this case) we simulate what happens directly after we change both inputs of a NAND SR flip-flop from 0 to 1 simultaneously. Fig.12 and Fig.13 show the results of running two simulations with the two outputs at initially 5V and 1nV less than Fig.9. LTspice schematic of two CMOS inverters in series. 5V (4.999999999 V) – trying both ways round. This tiny difference is sufficient to determine the final state of the circuit (which output goes to logic 1 (5V) and which to logic 0 (0 V)). The output which starts at the very slightly lower voltage ends up at 0. There are a couple of key things to note here. First, there is no oscillation, unlike that predicated by the digital gate model with equal delays (and Ken’s simulation). Second, the two voltages remain very close for a long time compared to the delay of the gates seen in Fig.10. It is more than ten times the 175ps propagation delay of the inverters before there is any significant voltage difference Fig.10. Simulation results for the circuit in Fig.9 showing an input change from 0 to 1 visible in Fig.12 and Fig.13. and the response of the two gates. every copy of the circuit we build behaves consistently, for example, because the circuit configuration ensures that one of the looped gates is (almost) always slowest. If this behaviour is in line with the design intention it could lead to a false sense of security – but the circuit may fail as a relatively rare event, or under certain conditions. If we look a little deeper at what is happening when we change both inputs of the NAND SR flip-flop from 0 to 1 simultaneously we find that the Boolean-function-plus-delay view of the logic gate does not really describe what happens. This may mean that a digital simulation (based on Boolean plus delay) fails to predict the behaviour of the circuit under the conditions we have been discussing. Some people may say that this means you should not trust the simulator – build the circuit instead. But building a prototype in which the design is inherently unpredictable may be equally misleading. If this copy behaves in a particular way, it does not mean that other copies will do the same thing. Metastability The behaviour seen in Fig.12 and Fig.13 is a form of what is known as ‘metastability’. As mentioned earlier, the circuit has two stable states, but it also has a metastable state in which the two inverters’ input/output voltages are equal. This is a point of perfect balance, like balancing a ball on the point of a needle – in theory it could stay there forever, but the situation is inherently unstable – a miniscule air current will cause the ball to fall off the needle, and likewise any small voltage perturbation will cause the circuit to fall into one of its two stable states. The response of metastable flip-flops can be analysed by solving differential equations describing the circuit behaviour. The results show that the more perfect the initial balance is, the longer it takes to exit from the metastable state (known as resolution time), and also that brief oscillations may occur for some circuits before the output stabilises. Analogue simulation Digital simulation simplifies the behaviour of logicgate basic circuits to allow very large and complex circuits to be simulated in a reasonable time. We can of course simulate relatively small digital circuits more accurately using an analogue simulator and a full transistor circuit schematic. We will look at an LTspice simulation of the circuits in Fig.4 and Fig.5 to gain some insight into what happens when we change both inputs of the NAND SR flip-flop from 0 to 1 simultaneously. We will just use inverters built from generic MOSFETs rather than attempt to model the full SR flip-flop used by Ken – this will be sufficient to illustrate typical behaviour. The circuit in Fig.9 is two CMOS inverters in series, Fig.11. LTspice schematic of two CMOS inverters in a loop. Note which we will use as a reference point when looking the .i c SPICE directive to set the initial voltage on the outputs. 48 Practical Electronics | February | 2021 Tracing the problem The reason that the Micro-Cap 12 simulation of Ken’s circuit shows an oscillation is because the inputs to an SR flip-flop can both change from 0 to 1 simultaneously and by default the simulation uses exactly equal delays for all the gates. Consider the SR flip-flop formed by X2 and X3. When the clock is 0 the set and reset inputs are both 1 via the inverter X8 and the NAND gate X1, which are driven by the clock. When the clock is 1 the inputs to the SR flip-flop are S=OUTX (via X4 and X1) and R=0 (via X8). If OUTX is 0 Fig.12. Simulation of the circuit in Fig.11 with initial conditions v(out1)=5 and when the clock changes from 1 to 0 v(out2)=4.999999999 the flip-flop’s inputs both change from 0 to 1 simultaneously. This initiates an oscillation due to the equal delays for X2 and X3, as described above. This situation is shown in Fig.14. This is a zoom-in on the results shown in Fig.2 with additional traces to show the outputs of gates X1 (N1) and X8 (N8). We see the clock (IN) changing from 1 to 0 followed by N1 and N8 both changing from 0 to 1 simultaneously one gate delay later. The oscillation starts in the SR flip-flop formed by X2 and X3 after another gate delay (trace for OUT). In the physical implementation of Fig.13. Simulation of the circuit in Fig.11 with initial conditions v(out1)= Ken’s circuit, the metastable condition in 4.999999999 and v(out2)=5 the X2/X3 flip-flop may not be triggered because it depends on the delays of X1 and X8 being close to Metastability may cause digital systems to fail. Unpredictable equal. Also, as we have seen, sustained oscillation is not likely outcomes and sustained intermediate voltage levels may result to occur in a real circuit if a metastable condition occurs – so in incorrect logic values propagating through the circuit. we would not expect to see this on the oscilloscope even if Even if the logic level from a metastable flip-flop finally ends there was metastability. If we assume the X1 and X8 delays up correct, if the resolution time is too long (eg, longer than are sufficiently different to not trigger the problem we can the clock cycle) errors will occur (eg, the wrong value is simulate the circuit under these conditions. We can do this sampled by a flip-flop connected to the metastable output). in Micro-Cap 12 by setting PARAMS:=MNTYMXDLY=1 for X8 to select the minimum timing delay model for the gate, rather than the default value. Double click X8 on the schematic to see and set the parameter settings. The results of this are shown in Fig.15 – the circuit operates as Ken intended and matches the results obtained from the real circuit. Questions Fig.14. Detailed look at the oscillation in Ken’s circuit. Practical Electronics | February | 2021 These results lead to questions about the simulation. First, is the simulation shown in Fig.2 wrong? We can say ‘no’ – the simulator has done exactly as was asked and simulated the circuit with all gates having exactly equal delays and the results are correct at the level of abstraction used. It does not accurately represent the analogue behaviour of the metastable flip-flop, but we would not expect this to be possible given the logic gate models used to ensure fast digital simulation. Second, the specific situation shown in Fig.2 is unlikely to occur in a real circuit, so we might also ask if the result is useful? Here we can say, ‘yes’; it alerts us to the fact that the circuit may suffer from a metastability problem. Knowing this we can decide about whether the risk of the problem occurring is acceptable or not, something which is dependent on the context in which the circuit will be used. Simulators are not the best tools for detecting timing problems, but software suites aimed at advanced digital design may include timing analysers, which detect possible timing problems, including metastability. 49 www.poscope.com/epe Fig.15. Micro-Cap 12 simulation results from the circuit in Fig.1 with the delay of X8 adjusted so that it does not match that of X1. (Compare with the original simulation of Fig.2 and working circuit of Fig.3.) - USB - Ethernet - Web server - Modbus - CNC (Mach3/4) - IO - PWM - Encoders - LCD - Analog inputs - Compact PLC Another question that arises is can we build a similar circuit which does not suffer from the problems discussed above? One possibility is to make use of the data latch shown in Fig.16. This also uses a NAND SR flip-flop to store data, but does so under the control of a clock. It is configured so that the S and R inputs of the SR flip-flop cannot be active at the same time. When the clock (Clk) is low, the two NAND gates connected to the clock force the S and R inputs to the inactive state (1). When the clock is high the D input is passed through to the S and R inputs, but the NOT gate ensures that only one of S or R is active. The flip-flop sets or resets depending on the D value. Using two of these latches in series with the output of the second latch inverted and fed back to the first creates a divide by two circuit, which is equivalent to wiring the Q output of a negative edge-triggered D-type flip-flop back to its D input. A D Q C lk Q Fig.16. Data latch using a NAND SR flip-flop. schematic for the suggested circuit is shown in Fig.17. This doesn’t include the NOT gates from Fig.16 because we can use the complementary outputs from the SR flip-flops. Simulation results are shown in Fig.18, where the divide-by-two operation can be seen. The circuit is not immune from metastability – it can be caused by changing the latch clock and data at the same time, but to achieve this we would have to clock the circuit fast enough for the delay through the latches to match the clock period. - up to 256 - up to 32 microsteps microsteps - 50 V / 6 A - 30 V / 2.5 A - USB configuration - Isolated PoScope Mega1+ PoScope Mega50 Fig.17. Divide-by-two circuit based on two D latches. - up to 50MS/s - resolution up to 12bit - Lowest power consumption - Smallest and lightest - 7 in 1: Oscilloscope, FFT, X/Y, Recorder, Logic Analyzer, Protocol decoder, Signal generator 50 Fig.18. Micro-Cap 12 simulation of the circuit in Fig.17 (all gate delays equal). Practical Electronics | February | 2021