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Circuit Surgery Regular clinic by Ian Bell Op amp offsets – Part 2 L ast month, we started to discuss op amp offsets in response to a question on the EEWeb Forum from user Deion about precision op amps. After quoting the OP97 datasheet from Analog Devices, Deion asked, ‘What confused me is the range of temperature? Should the resistor be balanced?’. We briefly considered the temperature range (this is stated on the device datasheet) and then looked at input offset voltage, the modelling of offsets, LTspice simulation of input offset voltage and the concept of noise gain. We will quickly recap some key points and then look at offsets due to bias currents flowing into the op amp – this is where we get to the question of balancing resistors, which Deion was asking about. Voltage offsets recap Use of input-referred voltages sources to represent offset and noise leads to the idea of ‘noise gain’. The noise gain of an op amp circuit is the gain which applies to a voltage applied directly to the op amp’s inputs. It is equal to the non-inverting gain – including circuits configured as inverting – as far as the signal is concerned. Even with a low offset op amp, users may want a circuit to have the facility to manually adjust the offset to minimise (or null) it. This feature is provided by some op amps, including the OP97. Typically, if offset adjustment is available, the op amp will have two pins labelled ‘Null’, to which a trimmer potentiometer is connected for offset nulling – the data sheet must be consulted for the exact details of how to do this for a given device. In simple terms, offsets are DC errors in a circuit’s output due to imperfections Bias currents in the circuit or components – they are When analysing op amp circuits, it is amplified and processed by the circuit often convenient to assume that no curcausing errors in the output. Offsets drift rent flows into the op amp. This is useful due to changes in temperature, aging and because it simplifies circuit analysis and other factors that influence the circuit. is often justified because the currents Offsets are important in DC and very low flowing into op amps in typical circuits frequency circuits because they cannot tend to be much smaller than the curbe blocked without blocking the wanted rents in external components such as signal. In other cases, unwanted DC output the gain-setting resistors. However, in may be damaging to a load intended to some cases the input currents cannot be be just driven by an AC signal. The only ignored as they can impact the perforsolution is to design circuits with inhermance of the circuit. ently low offsets. Op amps having low In a basic bipolar junction transistor offsets as a key characteristic are often (BJT) op amp circuit, current must flow referred to as ‘precision’ op amps, like into an op amp to bias the transistors the OP97 mentioned by Deion. in the input stage (to provide their base For an op amp, ideally, with a differencurrent). For FET-input devices the bias tial input of zero, the output should also currents will usually be much smaller as be zero, but with real op amps there will FETs do not have bias current into their typically be a non-zero output. The input gates; however, there will be leakage offset voltage (VIO) is defined as the DC voltage which must be supplied Op amp Ideal between the inputs to force the quiwith offset op amp escent (zero-input signal) open-loop – – VOut VOut VIn VIn output voltage to zero. For analysis – + + + purposes we can replace an op amp with an offset with an ideal op amp VOS plus an offset voltage source (see Fig.1). The offset (and other imper- Fig.1. An op amp with offset can be modelled as fections, such as noise) represented an ideal op amp with an offset voltage source at in this way is called ‘input referred’. its non-inverting input. 54 currents. For BJT circuits it is possible to include internal circuitry to deliver the bias, which greatly reduces the external currents. This means that the amount of current will vary significantly between different types of op amp. The input bias current (IIB) is defined as the average current into the two inputs (IB1 and IB2) with the output at zero volts (see Fig.2): IB = (IB1+IB2)/2 This can vary greatly for different types of op amp, from femtoamps (1fA = 10−15A) to tens of microamps, with tens to hundreds of nanoamps being typical for op amps with BJT input stages. Ideally, an op amp would have perfectly symmetrical inputs, which would therefore both take the same bias current; however, in the real world, the currents are different (either input may have the larger current). Input offset current (IIO) is defined as the magnitude of the difference between the currents into the two inputs with the output at zero volts: IOS = |IB1 – IB2| Bias currents, and offset current, will change with temperature – the temperature coefficient for these parameters will indicate the amount of change expected from a given op amp type. In a similar way to modelling the offset voltage with a voltage source and an ideal op amp (as shown in Fig.1) bias currents can be modelled with an ideal op amp and external current sources, as shown in Fig.3. For bias designated as flowing into the op amp, the current sources connect from the inputs to the most negative point in the circuit (typically negative IB1 IB2 – VOut + Fig.2. Input bias currents. Practical Electronics | March | 2022 IB1 IB2 Op amp with bias currents – considering situations such as the output voltage being limited by the supply (this would VOut be nonlinear behaviour). For linear circuits we can use superposition to deal with multiple sources – we set all sources except one to zero and find the effect of that source on its own (for example, its contribution to output voltage), then repeat with the other sources. Finally (because the circuit is linear) we can add up the individual contributions. We do not have to consider all the sources if we are only interested in the effects of one in particular. In this case we do not need to include the input voltage as the offset will just be added to the amplified input at the output (again linear behaviour) and we are only interested in the offset itself here. We start by finding the output voltage (in the circuit in Fig.4) due to IB1 (set IB2 = 0 and Vin = 0). The fact that IB2 = 0 means that the voltage across R3 is zero and hence the non-inverting input is at 0V. IB1 flowing in the resistors R1 and R2 will cause a non-zero voltage at the inverting input which will be amplified. Because the gain of the op amp is very large, the voltage across R2 (the output voltage) will be much larger than the voltage across R1 (the op amp input voltage). This implies that almost all of IB1 flows in R2. So, we assume that all of IB1 flows in R2, implying the voltage across it is IB1R2. One end of R2 is at Vout and we can assume the other end is at 0V because the voltage between an op amp’s inputs during normal operation in a feedback circuit is close to zero, and, as already noted, the non-inverting input is at 0V. So, the contribution to the output from IB1 is: R2 Ideal op amp – VOut + + IB1 IB2 VN Fig.3. Modelling input bias currents. supply or ground, VN in Fig.3). The sources cause the bias currents to flow in the external circuit as if they were being taken by the op amp’s inputs. The current sources are not connected to flow into the op amp itself. If this was done with a totally ideal op amp the current could not flow into the open circuit at the op amp’s input. If the op amp’s inputs are modelled with large input resistance then current forced to flow into the input would create a voltage drop which does not occur in a real circuit. Offsets due to bias currents Bias currents flow in the external components connected to the op amp (eg, the resistors used to set the gain) and so cause voltage drops. Differences in the bias currents for each input and/or the external impedance connected to the two inputs will cause these voltage drops to be different at each input. This difference will be amplified and appear as an offset voltage at the output. If we assume that the input offset current for an op amp is much smaller than the input bias current, then differences in voltage drops due to differences in external resistance may cause a significant offset. Under these circumstances the offset may be reduced by balancing the resistance at the two inputs – as mentioned in Deion’s question. For basic op amp amplifiers (standard inverting and non-inverting circuits) this can be achieved by adding a single resistor to one of the inputs Resistor balancing is illustrated Fig.4. The bias current to the inverting input flows through R1 or R2; so, making R3 equal to the parallel combination of R1 and R2 will result in the same voltage at the two inputs due to the bias currents (assuming the bias currents are equal). Resistor balancing We can analyse the resistor balancing requirement in more detail using some basic circuit theory, along with assuming the op amp is ideal apart from the bias currents. Referring to Fig.4, we note there are two sources of interest – the two bias currents – and we potentially also have the input voltage to take into consideration. We assume that the circuit is linear – the circuit is a linear amplifier, and we are not Practical Electronics | March | 2022 Vout = IB1R2 Next, we find the output voltage due to IB2 (set IB1 = 0 and Vin = 0). The current IB2 flows through R3 to produce a voltage of –IB2R3 at the op amp’s non-inverting input (negative because of the direction assigned to the current in Fig.4). Since the input of the circuit is connected to ground in this part of the analysis (Vin = 0) it behaves as a non-inverting amplifier as far as the voltage across R3 is concerned. The gain of this amplifier is found using the usual formula (A = 1 + R2/R1), thus the contribution to the output from IB2 is: VIn IB1 R1 IB2 Vout = IB1R2 – IB2R3(1 + R2/R1) VOut + R3 Fig.4. Minimising offset due to bias currents using resistor balancing in an inverting amplifier. Now, assuming IB1 = IB2 = IB and given that ideally we want Vout = 0, we put these conditions into the above equation. This means that IB can be cancelled to leave just a relationship between the resistors required to achieve Vout = 0 (zero offset), as shown below: 0 = IBR2 – IBR3(1 + R2/R1) IBR2 = IBR3(1 + R2/R1) R2 = R3(1 + R2/R1) R2 = R3(R1 + R2)/R1 To implement the resistor balancing we need to find the value of R3. We assume that we know R1 and R2 from designing the amplifier. Rearranging the resistor equation to make R3 the subject we get: R3 = R2R1/(R1 + R2) = R1||R2 Which you may recognise as the formula for two parallel resistors, which can be written using ‘||’ to mean ‘in parallel with’. Thus, R3 should be equal to the parallel combination of R1 and R2 for minimum offset. Inserting a resistor of this value between the non-inverting input and ground reduces the offset of an inverting amplifier (given the assumptions made above about the bias currents). Similarly, with a non-inverting amplifier, a resistor equal to the parallel combination of the two gainsetting resistors is inserted between the circuit input and the op amp input (R3 in Fig.5). The balancing resistors do not change the gain of the amplifiers. Balancing resistors work well if the magnitude of the input bias current is larger than the input offset current. The input offset current will limit the degree to which the input voltages can be balanced. However, R2 R1 – Vout = –IB2R3(1 + R2/R1) To find the total output due to the bias currents we add up these contributions: – VIn VOut + R3 Fig.5. Resistor balancing in a noninverting amplifier. 55 component attributes to Listing 1 set the level and change --- Operating Point --any other specific pa- V(in): 0 voltage rameters if required (as V(vp): 5 voltage shown last month). The V(vn): -5 voltage different model levels V(n003): -0.000909099 voltage now have their own V(n004): Update on the universal op amp -0.000909099 voltage component symbols V(out_balanced): Last month, we discussed the use of the -1.04308e-007 voltage (UniversalOpamp1, V(n001): UniversalOpamp2 component for mod-1.00025e-013 voltage UniversalOpamp2 … V(out_with_bias): 0.01 elling idealised op amps. We needed voltage and so on.) and there is V(n002): this to run simulations to illustrate the 0 voltage an additional level avail- V(out_ideal): use of an input-referred voltage source 0 voltage able (level 4). To fix the for modelling input offset voltage (as in error with the existing files it is necesFig.1). Models of real op amps would The output voltage for the ideal case sary to delete the old symbol and insert include internal modelling of their offis 0V (no offset). With the bias currents UniversalOpamp1 in its place and set sets, so adding the input referred voltage added the offset at the output is 10mV the component attributes (Avol and Rin source would end up modelling the offset (0.01) which is 100nV × 100kΩ: the voltmodel parameters) as discussed last month. twice, and we have no control over other age drop of the bias current flowing in the parameters. For investigations like this feedback resistor. Adding the balancing it is useful to have an op amp which is resistor reduces the offset to about 0.1µV Simulation example close to ideal in all aspects except the (−1.04308e−007) illustrating that under Fig.6 is an LTspice schematic of a circuit parameter(s) of interest, so you can obthe correct circumstances adding a balto illustrate bias current modelling and serve the effect(s) in isolation. ancing resistor can significantly reduce resistor balancing. Three versions of an The simulations in last month’s article offsets due to bias currents. inverting amplifier with a gain of 10 are were produced using a version of LTspice investigated. All three circuits use a closewhich had not been updated for a few to-ideal model of an op amp employing Internal input bias weeks, but an update was performed before the new UniversalOpamp1 component Successful use of a balancing resistor deworking on this article. This revealed that (level 1 op amp model) with parameters pends on the input voltage differences due the universal op amp component has adjusted to Avol = 100G and Rin = to the bias currents without the added resischanged recently – instead of one compo10GΩ, as discussed last month. The first tor being larger than any other effects that nent called UniversalOpamp2 there are circuit (using U1) has just the idealised might be caused with the resistor in place. now several versions of the component. op amp and gain-setting resistors. The This is not always the case in real circuits. The simulation files from last month may second circuit (using U2) models input The basic scenario (for a BJT op amp) is give an error (such as ‘Unknown subcircuit bias currents using current sources as disthat the bias currents are primarily due to called’) when used with the most up-to-date cussed above. The third circuit (using U3) the base currents of the op amp’s input tranversion of LTspice (from late 2021 onwards). adds a balancing resistor (RB3) equal to sistors, and these are well matched, so the As noted last month, the universal the parallel combination of the gain settwo bias currents are almost equal (IB much op amp component can model op amps ting resistors (10kΩ || 100kΩ = 9.091kΩ). larger than IOS). Fig.7 shows a very basic with different amount of detail as set The simulation runs an operating point differential amplifier which could be the by the ‘level’. Before the update there analysis which provides the results shown input stage of an op amp (real op amps are was one component and you had to edit above in Listing 1. more sophisticated, but this illustrates the point). With no signal (VIn1 and VIn2 at 0V) the current from the DiffAmpBias current source (IBDiff) splits equally between the matched transistors. For this current to flow in the emitters, base current must flow into the bases. The base current is IBDiff/2β, where β is the transistor’s current gain. This is the input bias current. Imperfect transistor matching will result in slightly different base currents, giving the offset current. Because the direction of bias current is fixed by the transistor type (NPN or PNP) the direction of Fig.6. LTspice simulation to illustrate bias current modelling and resistor balancing. the input bias current if the input offset current is small then the tolerance of the resistors may affect the level of balance that can be achieved (resistor variation will also result in voltage drop variation). 56 Practical Electronics | March | 2022 Listing 2 --- Operating Point 2 --V(in): 0 V(vp): 5 V(vn): -5 V(n003): 9.09099e-005 V(n004): 9.09099e-005 V(out_balanced): 0.00200001 V(n001): -9.99025e-015 V(out_with_bias): 0.001 V(n002): 0 V(out_ideal): 0 V(out_ideal): 0 will also be fixed. Typically, for this situation the input offset current will be ten or more times smaller than the input bias current and resistor balancing will probably work. However, some op amps have internal circuitry to supply the bias current – the bases of both input transistors are connected to current source circuits that supply (almost) exactly the required bias current – see Fig.8. The DiffAmpBias current source provides IBDiff to set up the emitter currents and the required base current (input bias current, IBin) is supplied by the InputBias1 and InputBias2 sources. The base current can be obtained by deriving half of IBDiff using the same reference as DiffAmpBias, passing this through a transistor matched to Q1 and Q2 and using its base current as a reference for the InputBias current sources. Balancing resistor fail For op amps with internal input biasing, the external current is the difference VCC R1 R2 Q1 Q2 VIn1 VIn2 IBdiff DiffAmpBias (current source) VEE Fig.7. Basic differential amplifier. VCC InputBias1 IBin R1 Internal bias current VIn1 (IBin) Q1 Base current IBin R2 Internal bias current (IBin) VIn2 Q2 Base current IBdiff External VEE bias current InputBias2 DiffAmpBias External bias current Fig.8. Differential amplifier with input bias current sources. Practical Electronics | March | 2022 between the supplied internal bias and the base current the transistor acvoltage tually takes (see Fig.8). voltage The specified op amp voltage input ‘bias current’ is this voltage small current difference, voltage not the full transistor bias, voltage but it is still referred to voltage as the input bias current voltage on datasheets. We have voltage a balance between two voltage almost equal quantities, voltage which are both subject to natural variation, so the average magnitude and amount of variability are of the same order and the input current to the op amp can be of either polarity. Op amps with internal input biasing tend to have similar values for input bias current and input offset current (IB similar to IOS). This means that adding a balancing resistor may make little or no improvement or may actually increase the offset at the output. As an example of this problem, if we rerun the simulation from Fig.6 with IB1_2 = IB1_3 = 10nA and IB2_2 = IB2_3 = −10nA to represent the possible behaviour of an op amp with internal input bias we get the results shown in Listing 2. In this case, adding the balancing resistor doubles the output offset from 1mV (0.001) to 2mV (0.00200001). For FET input op amps, the ‘bias’ currents are leakage currents from the input protection diodes and the FETs. These currents are typically much smaller than for BJT op amps but may increase significantly for input voltages near the supplies due to the behaviour of the protection diodes. For op amps with low input bias currents, any offsets caused by them may be significantly lower than offsets due to the input offset voltage. If this is the case then adding a balancing resistor will not make much difference to the overall offset, even if it does produce a small improvement. Another possible issue with adding a balancing resistor is that it will contribute random noise to the circuit. Larger resistors and larger circuit gains will result in more noise at the output. Noise from the balancing resistor is amplified by the circuit’s noise gain. In conclusion, balancing resistors may improve offsets, but it depends on the op amp and they are certainly not guaranteed to improve a circuit. Simulation files Most, but not every month, LTSpice is used to support descriptions and analysis in Circuit Surgery. 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