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By Andrew Levido Precision Electronics Part 7: Analog-to-Digital Conversion Last month, in the sixth instalment in this series, we covered the various sources of analog-to-digital and digital-to-analog conversion errors. We also looked at digitalto-analog converters (DACs) in detail. This month, we will focus on analog-to-digital converters (ADCs) and, as usual, that will include a practical example. J ust as a quick recap, we saw that all converters exhibit quantisation errors due to the discrete way numbers are represented in digital systems. Quantisation error is directly related to the number of bits (the resolution) of the converter. We saw that this can cause quantisation noise if we are dealing with AC signals. On top of quantisation errors, we saw that there are usually offset, gain and non-linearity errors associated with conversion and that these can be combined to give a total unadjusted error (TUE) figure that can be used in error calculations. All of this applies equally to DACs and ADCs. Sampling and aliasing In contrast to DACs, which convert discrete digital codes to discrete voltage levels, ADCs have to convert an infinitely variable (and maybe varying) voltage level to discrete digital codes. We therefore have to ‘sample’ the analog voltage at some instant in time and convert that value to the appropriate (nearest) digital code. Because the conversion takes a finite amount of time, in most instances, we want to take a ‘snapshot’ of the input voltage so that the entire conversion process takes place with a fixed input value. For this reason, many converters (but not all, as we shall see below) are preceded by a ‘sample-and-hold’ circuit similar to that shown in Fig.1. The output of the sample-and-hold buffer follows the input during the sampling period, when the switch is closed. It is held constant by the capacitor during the hold period, while the switch is open. The conversion takes place during the hold period while the value is stable. In Fig.1, I have shown the sample and hold’s output (red trace) instantaneously snapping back to track the input voltage when the switch is closed. In reality, the capacitor takes a finite time to charge or discharge. If your ADC has a sample-and-hold system, you need to make sure the sampling time is long enough for the capacitor to fully charge to the signal voltage through the signal’s source impedance. This source impedance can include the sample-and-hold switch on-­resistance, the on-­resistance of any analog multiplexer, and the external source impedance. Values in the kilohms range are not unusual. The sampling time should be long enough for the capacitor voltage to Fig.1: the output of a sample-and-hold circuit follows the input while the switch is closed, but ‘freezes’ the value while it is open. This allows the analog-to-digital conversion process to occur with a steady input voltage. 88 Silicon Chip Australia's electronics magazine charge or discharge to within ½LSB (least significant bit) of the signal voltage to avoid adding error to the conversion. Many ADCs allow the user to control the sampling time for this purpose. Assuming we want to perform the analog-to-digital conversion on an ongoing basis, we need to sample and convert the input signal at regular intervals. We call these intervals the sampling rate. The Nyquist-Shannon sampling theorem states that an AC signal can be fully reconstructed (without any loss whatsoever) so long as the sampling rate, fsamp, is at least twice the highest frequency component present in the signal (fmax). The particular sampling rate that is exactly twice fmax is the known as the Nyquist frequency, fn. If we sample at a higher rate than strictly necessary (fsamp > fn), we are said to be oversampling, while if we sample at a lower rate (fsamp < fn), we are undersampling. We often want or need to oversample, but we generally try to avoid undersampling as it can lead to a phenomenon called aliasing, which can give rise to significant errors. Fig.2 shows what can happen if we Fig.2: here a 1kHz signal is sampled at 1.25ksps, lower than the Nyquist limit of 2ksps. This results in the ADC measuring a 250Hz alias signal instead of the expected 1kHz signal. siliconchip.com.au undersample a signal. Here, a 1kHz sinewave (shown in blue) is sampled at about 1.25ksps – lower than the Nyquist frequency of 2ksps. The sample points (red dots) trace out a false ‘alias’ signal with a frequency of 250Hz. Within the digital system, we will have no idea that the true signal includes a 1kHz component and that the 250Hz signal is an alias – all we will measure is the 250Hz sinewave. To avoid aliasing, we must ensure that there is no content in the sampled signal with a frequency higher than ½fsamp. This can be achieved by limiting the bandwidth of our signal with a filter, or by using a high enough sampling rate. In practice, we often need to do both. For wideband signals, it can be difficult or impossible to totally eliminate aliasing since perfect ‘brick wall’ filters are hard to come by! Instead, we have to be satisfied with reducing the amplitude of the worst possible alias to something we can live with. It is easiest to understand this in the frequency domain, as shown in Fig.3. In each diagram, the vertical axis is the relative amplitude of the signal in decibels (dB), while the horizontal axis is the frequency on a linear scale. We are interested in digitising a broadband signal within the band of interest shown shaded in blue. Because the signal is broadband, we apply some low-pass filtering with corner frequency fc, shown by the solid curve. The dotted lines represent the magnitude of the alias signals obtained by reflecting the filter roll off about the Nyquist limit (½fsamp). If the filter had a ‘brick wall’ cutoff, there would be no aliasing. Silicon Chip kcaBBack Issues $10.00 + post $11.50 + post $12.50 + post $13.00 + post January 1997 to October 2021 November 2021 to September 2023 October 2023 to September 2024 October 2024 onwards In the first diagram, we try to eliminate aliasing by adding a second-­ order low-pass filter, with its corner frequency set at the upper end of the bandwidth of interest, and by oversampling by 50% (the Nyquist limit is set 50% higher than the upper limit of the band of interest). You might think that this would be enough to eliminate aliasing, but unfortunately, it is not. The dotted line shows that there will still be an alias component within the band of interest, although it will be 6dB or more below the level of the signal of interest. This happens because there is still content in the low-pass filtered signal with frequency components above the Nyquist limit, albeit at a low level. The second chart shows that using a fourth-order filter, with its steeper roll-off, helps by shifting the alias signal down to -16dB or lower. We could improve this even further by using a sixth- or eighth-order filter, at the expense of complexity. The final chart shows what happens if we retain the fourth-order filter but increase the sampling rate to oversample at 100%, rather than the 50% in the first two cases. The alias signal is now down by 30dB or more. The long and short of this is that if you are digitising signals with a broadband AC component, you need to choose your sampling rate and filter All back issues after February 2015 are in stock, while most from January 1997 to December 2014 are available. For a full list of all available issues, visit: siliconchip.com.au/Shop/2 configuration carefully to ensure you don’t introduce errors due to aliasing. You don’t have to eliminate the aliases entirely – you just need to get them down to a level where the errors from them are manageable. You may not need an anti-aliasing filter or oversampling if your signal is band-limited by its very nature. If your signal is nominally DC (or at least very slowly changing), you can be even more relaxed about choosing the sampling rating and anti-aliasing filter. Flash ADCs With anti-aliasing taken care of, and a sample-and-hold system keeping our ADC’s input constant while sampling, we are ready to actually convert our analog signal to a digital one. The most straightforward way to do this is the ‘flash’ or parallel ADC, a simple threebit example of which is shown overleaf in Fig.4 (this is not directly related to flash memory). A resistor string establishes a series of threshold voltages representing the transition voltages between each code. The input voltage is simultaneously compared to all of these thresholds. A comparator output will be asserted low if the input voltage exceeds the respective transition threshold. A priority encoder outputs the code associated with the highest-­value input that is asserted. Fig.3: using a higher-order low-pass filter and increasing the sampling rate can both help reduce aliasing when digitising broadband signals. siliconchip.com.au Australia's electronics magazine May 2025  89 True flash converters require 2n matched resistors and the same number of comparators (where n is the resolution in bits), so they are usually limited to about 16 bits, but they are very fast. They can make a conversion every clock cycle, so they can reach sampling rates in the Gsps (gigasamples per second or 1,000,000,000+ samples per second) range. Many modern flash ADCs use a multistage architecture with a series of lower bit-count flash conversions of increasing precision. These ‘pipelined’ flash converters can have a latency of several tens of clock cycles, but maintain conversion rates in the Gsps range, since sequential samples are being processed in each stage. Several flash ADCs can be interleaved to achieve even higher sampling rates. If you have a digital oscilloscope (DSO), it most likely uses a pipelined flash converter with eight, 10 or 12 bits of resolution and a multiGsps sampling rate. Successive approximation Successive approximation analog-­ to-digital conversion uses a binary search strategy to find the digital code corresponding to the analog input. A simplified three-bit successive approximation converter is illustrated in Fig.5. At the start of the conversion cycle, the controller clears the successive approximation register and sets its MSB to one. The output of the DAC will therefore be a voltage that is 50% of the full scale. The comparator checks if the input voltage is above or below this threshold. If it is above 50% (comparator output high), the MSB in the SAR remains set; otherwise, it is cleared. The controller then sets the next most significant bit so the DAC and comparator can check if the input voltage lies in the upper or lower part of the appropriate sub-range. Again, the bit remains set or is cleared based on the comparator output. This process continues bit-by-bit until the value of the least significant bit is confirmed. At this point, the controller latches the SAR contents through to the converter output, and the cycle can begin again. This binary search process is shown graphically on the right side of Fig.5. Starting with the MSB, each bit is set or cleared successively until the output code is complete. This iterative approach means that the conversion takes at least one clock cycle for each bit, so SAR converters are generally slower than flash converters, with conversion rates typically limited to the Msps (megasamples) range. This is the type of converter you will usually find in microcontrollers and many low-cost serial interface ADC chips. Integrating converters Fig.4: a ‘flash’ ADC compares the input signal to each threshold voltage simultaneously. The output is the digital code associated with the highest threshold the input signal reaches. 90 Silicon Chip You can see why a sample-and-hold system is important if you are using a successive approximation ADC. If the value of the input were to change mid-conversion, the result could be a wrongly set bit and therefore a potentially significant error. However, there is a class of converter – the integrating converter – that can accommodate a changing input during the conversion cycle. In fact, we can use this characteristic to our advantage. Australia's electronics magazine The simplest integrating converter is the single-slope variant shown in Fig.6. When the start signal is pulsed, the flip-flop is set, the transistor is switched off and capacitor C begins to charge linearly at a rate determined by the value of the current source. Simultaneously, the clock is gated through to the counter, which begins counting up. When the voltage on the capacitor rises to Vin, the comparator resets the flip-flop and stops the counter, which holds a number proportional to the time taken to charge the capacitor to Vin. The count time is given by Tcount = C × Vin ÷ I and the count value will be N = (C × Vin) ÷ (I × Tclk), where Tclk is the clock period. The output count is therefore dependent not only on Vin and the current I but also on the capacitor value and the precision of the clock frequency. The latter two are a bit of a problem, since tight tolerance capacitors are rare and expensive, and very precise and stable clocks are not easy to create. Fortunately, a variation on this scheme – the dual-slope converter – solves these problems very elegantly. Fig.7 shows how it works. This time, the controller first charges the capacitor up for a fixed period (Tcharge) with a current proportional to the input voltage. The capacitor is then discharged by a fixed current of Idis, and the time taken for the capacitor voltage to ramp down to zero (Tcount) is measured by the counter. If we allow the capacitor to charge for M clock cycles, its voltage will reach Vcap = Iin × M × Tclk ÷ C. The count required for the capacitor to discharge from Vcap to 0V will be N = C × Vcap ÷ (Idis × Tclk). As Vcap is the same for both charge and discharge phases, we can substitute the first equation into the second. The capacitor value and the clock period cancel out, and we are left with N = M (Iin ÷ Idis). Recalling that Iin is proportional to Vin, we can see the count N is proportional to Vin, Idis and some constants. The conversion precision is therefore not dependent on the capacitor’s value or the clock frequency. As a bonus, any offset error in the comparator is also eliminated since the charge-discharge cycle will start and end at the same voltage, even if it is not precisely zero. siliconchip.com.au Fig.5: a successive approximation ADC uses a binary search algorithm to determine the state of each successive bit, starting with the MSB (most significant bit). Fig.6: a single-slope integrating ADC measures the time taken to charge a capacitor up to the input voltage using a known current. Achieving high precision requires a stable clock and a precise capacitor value. The only requirement is to use precision current sources and a capacitor with low dielectric absorption (a polypropylene dielectric is a good choice). Dielectric absorption is the mechanism responsible for the ‘memory effect’ in capacitors, where a recently discharged capacitor recovers some voltage over time after being discharged. This would obviously lead to errors in the dual-slope converter. The ‘integrating’ nature of the charge cycle explains why dual-slope ADCs don’t generally need a sample-andhold circuit. Any changes in input voltage are averaged out over the capacitor charge period. This means integrating converters are inherently low-pass filters, so they work best with DC or very low-frequency signals. An anti-aliasing filter is not normally required for the same reason. You can take advantage of this averaging to very effectively reject any mains-frequency interference that might be present on your signal. By setting the charge time to an integer multiple of the mains cycle period (20ms for 50Hz mains), any mains component present at the input will be averaged to zero over one or more full cycles. Being counter-based, integrating ADCs are quite slow, but with resolutions of 20 or more bits (better than 1ppm resolution), and the ability to effectively reject mains interference, they are widely used in test and measurement equipment like digital multimeters (DMMs). Very high-end test equipment (6½ or 7½ digit multimeters, for example) use more advanced variants known generically as multi-slope converters. Each manufacturer has their own proprietary flavour, but they all rely on the same charge-balancing principle. Delta-Sigma ADCs Another type of ADC that has come to the fore in recent years is the delta-­ sigma converter. A delta-sigma ADC consists of an analog modulator that produces a single bit stream, followed by a complicated digital filter. The inner workings of delta-sigma ADCs are not easy to describe or understand – so bear with me as I give it a shot. We will start with the modulator, which is where the magic happens. The upper part of Fig.8 shows a simplified first-order modulator. Practical ADCs use higher-order modulators, but the principles remain the same. The input is an analog voltage in the range ±V with a maximum frequency Fig.7: the dual-slope integrating ADC has the advantages of not being dependent on either a precise capacitor value or clock frequency. Its integrating nature also allows it to be configured to reject mains interference. siliconchip.com.au Australia's electronics magazine May 2025  91 Fig.8: the delta-sigma ADC consists of a modulator that produces an oversampled bit stream followed by a complex digital filter. These ADCs can have up to 32 bits of resolution and sampling rates in the Msps range (although not at the same time). component of fmax. The modulator is clocked at a rate higher than 2fmax by an oversampling rate factor (OSR). We will assume the OSR is 128 for the purposes of this example. The clock frequency is therefore 256fmax. The output of the modulator is a stream of 1s and 0s at the clock frequency, where a 1 code corresponds to V+ and a 0 code corresponds to V–. The average value of this bit stream over many cycles is equal to Vin. For example, a zero-volt input would be represented as a string of alternating 1s and 0s corresponding to alternating V+ and V– voltages, averaging to 0V. The example waveforms to the right of the figure show what happens with an input voltage of ¼V+. In the initial clock cycle, the bit stream value is zero, and the switch directs a voltage of V– to the summing junction, where it is subtracted from the input voltage. The resulting voltage (5/4V) represents the ‘error’ between the input and the reconstructed modulator output (this is the ‘delta’ part of the delta-sigma converter). This error is integrated (the ‘sigma’ part) and the comparator determines if the result is positive or negative. In our example, the result transitions from negative to positive about ¼ of the way through the clock cycle. On the next clock edge, a one is latched into the bit stream. The error voltage swings to -3/4V, and the 92 Silicon Chip integrator starts to ramp down. The result is still positive at the end of this cycle, so the comparator output stays high and the third bit in the stream is also a 1. This process continues indefinitely, producing a bit stream with five 1s and three 0s for every eight bits, as shown. Since we want to provide an output code at the sampling frequency (2fmax), we have to do it every 128 clock cycles. There can therefore only be 128 possible discrete values in the bit stream for each sample (128 zeros to 128 ones). If this was all there is to it, we would have created a 7-bit converter, which is pretty unexciting. However, the delta-­ sigma converter has a trick or two up its sleeve. The filter component of the ADC is a digital filter called a Finite Impulse Response (FIR) filter. We could write a whole series of articles on digital filters, but for a one-bit input this just consists of a long shift register with each output enabling or disabling a coefficient (a carefully chosen number) depending on whether it is a one or a zero. All the coefficients are summed on each clock cycle to produce a digital output code. The coefficients are chosen to produce a very steep low-pass filter, with a cutoff frequency of fmax. The output is decimated so that the resulting number changes only once for each sampling period. Decimation in our example just means each 128th Australia's electronics magazine sample is sent to the output and the other 127 are thrown away. The filter coefficients have a resolution much higher than seven bits, and there may be many hundreds or even thousands of coefficients in the filter. This means each output code can take significantly more than 128 different values and, therefore, it has much more than seven bits of resolution. If you find this last part hard to grasp, you are not alone. The mathematics behind it is complex, and some of the explanations you will find are confusing. Another way to look at it is to think of the modulator as a ‘perfect’ ADC with significant quantisation noise superimposed on it. The oversampling nature of the modulator is such that this noise is ‘shaped’ (pushed up) to frequencies well above the sampling rate. The low-pass filter then blocks most of this noise, leaving a level of quantisation noise corresponding to many more bits of resolution than the oversampling rate would suggest. Delta-sigma ADCs offer excellent performance at reasonable prices. Audio ADCs can easily have 24-bit resolution and sampling rates of 96kbps or 192kbps, with extremely low distortion. Precision DC-accurate delta-­ sigma converters with up to 32 bits of resolution are available (at a price). Delta-sigma ADCs are available with sampling rates up to 20Mbps. One of siliconchip.com.au the big advantages of delta-sigma converters is their inherently high oversampling rate means that anti-aliasing filtering is made easier. chip bandgap reference with a nominal 1.2V value and ±100ppm/°C tempco. At manufacture, the value of this internal reference is read by the ADC while the chip is supplied with a preA practical example cise supply voltage (3.0 ±0.01V). The I am developing a project that uses a resulting code is burned into non-­ low-cost microcontroller with a 12-bit volatile memory on the chip. You can successive approximation ADC to use this to convert a supply-referenced measure a ±6V analog signal. We will ADC reading to an absolute voltage use this example to see what kind of with known precision. performance we can expect from this The ADC also includes an auto-­ pretty common scenario. calibration feature that automatically The microcontroller I have chosen performs a zero calibration. This only is the STM32L031, a low-power, low- works to eliminate on-chip offset pin-count unit with a Cortex M0+ CPU errors, such as those related to the anacore. It has a built-in 12-bit ADC with log multiplexer, the sample-and-hold a maximum sample rate of 1.1Msps system and the ADC itself. If you want that uses the microcontroller’s power to eliminate off-chip offset errors, you rail as its reference. need to provide the hardware and do The ADC’s headline specifica- this yourself, as we discussed in the tions are modest, with a worst-case third article in this series. offset error of ±2.5LSB, a worst-case In addition, the ADC includes an gain error of ±2.0LSB and an INL of oversampler that automatically makes ±2.5LSB for a TUE of just over ±4LSB. several sequential conversions (up to Data sheet typical values are about half 256), sums the result, then scales the of these figures, but you already know result back by some factor to get an how I feel about typical values. averaged result. Of course, you could This would mean that the lower do this in firmware, but the hardware two bits of the result probably should oversampler does everything in the not be trusted, making this effectively background for you. a 10-bit converter, unless we can do This technique can actually improve something to improve its performance. the precision of ADC measurements in The ADC does have some nice fea- the presence of noise. This means that tures. One of the downsides of micro- a 12-bit ADC could appear to have 13 controller ADCs is that they use the or more bits of precision. power rail (or, if you are lucky, a dedThe reason this works is shown in icated analog supply pin) as the full- Fig.9. Here, we have a noisy signal scale voltage reference. Since I am with an average value between the powering this device from a 3V coin nth and nth+1 thresholds of an ADC. cell and boost converter, the power rail If we were to take just one sample, we is neither very precise nor very stable. could get either result. In fact, it is posThe STM32L031 includes an on-­ sible we could get a result one more bit higher and lower if we are unlucky with our sampling. If we make many measurements, however, some will be high and some low, but their average will lie somewhere between the two thresholds. We could say the resulting measurement is at the nth+½ threshold, effectively giving us an extra bit of resolution. This only works if the noise has an average value of zero and is uncorrelated with the sampling rate, and the noise has to have sufficient magnitude. Sometimes, a designer will deliberately introduce noise or some other form of ‘dither’ to a signal to increase the resolution when oversampling. Design decisions The relevant part of the test circuit I built is shown in Fig.10. The challenge is to digitise a bipolar (in this case, ±6V) signal with a single-ended ADC and a single 3.3V supply. The input signal is coupled to the ADC by a difference amplifier with a gain of 0.25, reducing the 12V input span to 3V, within the ADC input range. Using a difference amp here allows the input voltage to extend well beyond the supply rails without getting into problems with an op amp’s common-mode input range. The reference input of the difference amplifier is connected to the mid-point of the power supply derived from a voltage divider and buffer op amp. The output of the difference amplifier will therefore Vout = 0.25 (Vin+ – Vin–) + 1.65V. This means the voltage applied to the ADC will be in the range 1.65 ±1.5V (0.1V to 3.2V) over the ±6V input span, Fig.9: it is possible to increase the effective resolution of an ADC for slowly changing signals by averaging many samples of a noisy signal. Fig.10: the test circuit digitises a ±6V input using a difference amplifier with a gain of 0.25 and an offset of about 1.65V. The latter value is not critical, since this voltage is also digitised and the measured value is used to reconstruct the input voltage. siliconchip.com.au Australia's electronics magazine May 2025  93 avoiding the ends of the ADC input range near the supply rails where we know errors may lie. I have used lowcost TP5534 zero-drift op amps and 0.1% gain setting resistors to keep the analog errors down. The error budget table (Table 1) shows the analog error (line 5) is around ±0.2% in the worst case – almost all down to the gain resistor tolerance. The offset errors in lines 1 and 2 of the table are very low, so the internal zero calibration should be sufficient for our purposes. It is probably not worth using higher precision resistors here, since the ADC and calibration errors are of a similar magnitude. The ADC TUE of ±4LSB corresponds to a relative error of just over 0.1% and an absolute error of ±3.2mV. The relative error is easy to calculate from the TUE and the ADC precision: 100% × TUE ÷ (2n – 1), where n is the ADC precision in bits. We don’t need to use precision resistors to create the mid-supply voltage since we also digitise this voltage and subtract it in firmware. The absolute value of the mid-point voltage therefore does not matter – it just has to be close to half the supply voltage. I set the ADC up with an 8MHz clock giving a cycle time of 125ns. A single conversion consists of a sampling period, which is programmable, and a conversion time of 12.5 clock cycles. I chose a sampling time of 19.5 cycles (about 2.5µs) to be 10 or more times longer than the time constant of the external RC filter, and that of the internal filter made up of the 8pF sampling capacitor and the 1kW resistance of the analog multiplexer and sampleand-hold switches. I configured the oversampler to take 256 samples and to divide the resulting sum by 256 to restore 12 bits of resolution. There is no point in going for higher resolution, since the analog errors and the ADC TUE are already at this level of precision. No amount of oversampling will compensate for errors that affect every sample to the same extent. We use the same oversampling on all three ADC conversions: the main input, the mid-supply offset and the internal voltage reference. I also performed an internal zero-calibration on initialising the ADC to make sure any offset errors in the input multiplexer and sample and hold were minimised. Scaling the ADC results The relationship between the ADC code N and the absolute voltage on an ADC pin is Vin = Vdd (N ÷ 4095), where Vdd is the microcontroller’s power supply voltage. We don’t know this voltage precisely, but we can work it out by using the ADC to read the internal reference (NIREF) and the stored ADC code (NCAL) that was converted with a known supply voltage: Vdd = 3.0 × (NCAL ÷ NIREF) Having calculated the absolute voltage of the input and the midpoint offset voltage (in millivolts, since we are dealing with integers), we can use these, plus the nominal differential amp gain, to calculate the overall circuit input voltage. I did all of this and measured the input voltage, the ADC channel input voltage and read out the digital result. The results are pretty impressive – the measured error is better than ±0.05%, corresponding to ±3mV on the fullscale ±6V input range. This is 1 part in 2000, or about 11 bits of effective resolution. The transfer function of the ADC turned out to be f(x) = 0.9995x – 0.0002 with an R2 of 1.000. The line-of-bestfit gain error is less than ±0.01% and the offset error is less than 1mV. The worst individual sample error was better than ±0.05%. These results are an order of magnitude better than the 0.6% error calculated in the error budget. To some extent, this is to be expected (the odds are low that we will have the worstcase errors everywhere), but it is worth a bit of a closer look at why it performs better than expected. First, the calculated analog gain error is almost all due to the resistor tolerances, which would have to all be at the extremes of their tolerance band – that is unlikely in practice (but possible, of course). Second, the calculated TUE includes offset error, which is nulled out through the zero-calibration process. And finally, the 0.3% error on the supply voltage for the factory calibration seems to me to be a very conservative figure. I would be surprised if the supply voltage was not regulated more tightly than ±10mV during this step, so will probably be better than specified by an order of magnitude. So, in conclusion, the typical 10to 12-bit ADCs used in microcontrollers are really useful, but they have some limitations – especially if you are using the power supply voltage as the reference. Read the data carefully, since they will likely have fewer bits of effective resolution once the TUE is taken into account. To most effectively use the bits at your disposal, you should think seriously about averaging many samples if your microcontroller has the time to do so. That depends on how quickly your input is changing, how fast your ADC is, how many measurements you have to make, how often and so on. As I have mentioned before, in precision applications, you should also avoid using the very ends of the ADC SC span. Table 1: ADC (analog-to-digital converter) error budget Error Source (25˚C) Nominal Value Absolute Error Relative Error 1 Op Amp Offset Voltage (±20µV, 0.05µV/˚C) 0V 20μV 0.000% 2 Voltage due to Op Amp Offset Current (±100pA, 300kW || 1.2MW) 0V 24μV 0.000% 3 Total error at Op Amp Input (Line 1 + Line 2) 0V 44μV 0.001% 4 Op Amp Gain Error (0.1% resistors) 1.25 5 Voltage error at ADC Input (Line 3 × Line 4) 0V 12mV 0.201% 6 ADC (TUE ±4LSB – least significant bits) 0V 3.2mV 0.107% 7 Total error in ADC code (Line 5 × Line 6) 0V 10.2mV 0.308% 8 Error in internal Vref calibration (<at>3.0±0.01V) 0V 10mV 0.303% 9 Total error (Line 7 × Line 8) 0V 20.2mV 0.611% 94 Silicon Chip Australia's electronics magazine 0.200% siliconchip.com.au